According to an aspect of the present disclosure, a semiconductor device includes a semiconductor substrate, a lower electrode provided on the semiconductor substrate, an insulating film that is provided on the semiconductor substrate and surrounds the lower electrode and a metal film that is provided on the lower electrode and includes a convex portion on an upper surface thereof, wherein the convex portion includes a first portion extending in a first direction parallel to an upper surface of the semiconductor substrate, and a second portion extending in a second direction that is parallel to the upper surface of the semiconductor substrate and intersects the first direction, and the metal film is thinner than the insulating film.

The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.

A semiconductor substrate has, on an Au electrode pad, an electrolessly-plated Ni film/an electrolessly-plated Pd film/an electrolessly-plated Au film or an electrolessly-plated Ni film/an electrolessly-plated Au and a method of manufacturing the semiconductor substrate by the steps indicated in (1) to (6) below: (1) a degreasing step; (2) an etching step; (3) a pre-dipping step; (4) a Pd catalyst application step; (5) an electroless Ni plating step; (6) an electroless Pd plating step and electroless Au plating step or an electroless Au plating step.

A semiconductor chip includes a redistribution layer having an improved reliability. The semiconductor chip includes a device layer on a semiconductor substrate, a wiring structure on the device layer, a cover insulating layer on the wiring structure, and a redistribution layer. The device layer includes a semiconductor device. The wiring structure includes an internal connection pad electrically connected to the semiconductor device. The cover insulating layer includes a first recess filled with a connection via connected to the internal connection pad and a second recess having a depth that is less than that of the first recess. The redistribution layer in connected to the connection via and extends along an upper surface of the cover insulating layer.

A low stress moisture resistant structure of semiconductor device comprises a low stress moisture resistant layer, wherein a semiconductor device is formed on a semiconductor wafer, the semiconductor device comprises at least one pad, the low stress moisture resistant layer is coated on the semiconductor device and the semiconductor wafer so that a pad top center surface of the pad is exposed. The low stress moisture resistant layer comprises a material comprising crosslinked fluoropolymer. A before-coated stress measured on the semiconductor wafer before the low stress moisture resistant layer is coated and an after-cured stress measured on the semiconductor wafer after the low stress moisture resistant layer is coated and cured define a stress difference, the stress difference is greater than or equal to 510.sup.7 dyne/cm.sup.2 and less than or equal to 510.sup.7 dyne/cm.sup.2.

A low stress moisture resistant structure of semiconductor device comprises a low stress moisture resistant layer, wherein a semiconductor device is formed on a semiconductor wafer, the semiconductor device comprises at least one pad, the low stress moisture resistant layer is coated on the semiconductor device and the semiconductor wafer so that a pad top center surface of the pad is exposed. The low stress moisture resistant layer comprises a material comprising crosslinked fluoropolymer. A before-coated stress measured on the semiconductor wafer before the low stress moisture resistant layer is coated and an after-cured stress measured on the semiconductor wafer after the low stress moisture resistant layer is coated and cured define a stress difference, the stress difference is greater than or equal to 510.sup.7 dyne/cm.sup.2 and less than or equal to 510.sup.7 dyne/cm.sup.2.

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.

A semiconductor package includes a semiconductor chip, and including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad of the semiconductor chip and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening, an encapsulant covering at least a portion of the semiconductor chip, and a connection structure disposed on the active surface of the semiconductor chip, and including a connection via connected to the connection pad in the first opening and the second opening and a redistribution layer electrically connected to the connection pad through the connection via. The second opening has a width narrower than a width of the first opening.

A package includes an electronic chip having a pad. The pad is at least partially covered with adhesion enhancing structures. The pad and the adhesion enhancing structures have at least aluminium in common.

The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.