A semiconductor interconnect structure including a conductive layer, a plurality of interconnect vias and a pad is presented. The interconnect vias are formed over the conductive layer and the pad having a substantially flat surface is formed over the plurality of interconnect vias. The conductive layer may be a conductive line and/or a conductive plate connected to a conductive line.

An optical sensor includes a bare chip mounted on a circuit board, a protection member configured to protect the bare chip, a pad connected to the bare chip via a wire, and a pattern connecting the pad and a terminal portion at an edge of the circuit board to each other. The pattern is connected to the terminal portion on a same surface as a surface on which the bare chip is mounted, and a portion of the pattern between the protection member and the terminal portion is covered with solder resist.

In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding.

A semiconductor package includes a semiconductor chip including a body, a connection pad, a passivation film, a first connection bump disposed, and a first coating layer; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure including an insulating layer, a redistribution layer, and a connection via. The first connection bump includes a low melting point metal, the redistribution layer and the connection via include a conductive material, and the low melting point metal has a melting point lower than a melting point of the conductive material.

In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect layer over the substrate. The chip structure includes a conductive pad over the interconnect layer. The chip structure includes a conductive bump over the conductive pad. The conductive bump has a first portion, a second portion, and a neck portion between the first portion and the second portion. The first portion is between the neck portion and the conductive pad. The neck portion is narrower than the first portion and narrower than the second portion.

An optical sensor includes a bare chip mounted on a circuit board, a protection member configured to protect the bare chip, a pad connected to the bare chip via a wire, and a pattern connecting the pad and a terminal portion at an edge of the circuit board to each other. The pattern is connected to the terminal portion on a same surface as a surface on which the bare chip is mounted, and a portion of the pattern between the protection member and the terminal portion is covered with solder resist.

A semiconductor fabrication apparatus has a transfer plate having a plurality of transfer pins to transfer a flux onto a plurality of lands on a semiconductor substrate, a holder movable with the transfer plate, to hold the transfer plate, a positioning mechanism to perform positioning of the holder so that the plurality of lands and the respective transfer pins contact each other; and a pitch adjuster to adjust a pitch of at least part of the plurality of transfer pins.

A semiconductor device includes a bonding pad that includes a base portion having a base layer. A bond wire or clip is bonded to a bonding region of a main surface of the bonding pad. A supplemental structure is in direct contact with the base portion next to the bonding region. A specific heat capacity of the supplemental structure is higher than a specific heat capacity of the base layer.