A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.

The present application discloses a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes providing a substrate, forming a pad structure above the substrate, and forming a top groove on a top surface of the pad structure.

A semiconductor package and a method of making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor packages, and methods of making thereof, that comprise a conductive layer that comprises an anchor portion extending through at least one dielectric layer.

A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

A method of fabricating a semiconductor structure includes: forming a conductive layer on a first insulating layer; etching a portion of the conductive layer to expose a portion of the first insulating layer; deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; and removing a residue of the conductive layer on the rough surface of the first insulating layer.

A semiconductor package includes a semiconductor substrate, an interconnect structure disposed over the substrate, a first passivation layer disposed over an interconnect structure, a contact pad disposed over the first passivation layer, a dummy pattern disposed around the contact pad and over the first passivation layer, and a second passivation layer overlaying the dummy pattern and the contact pad.

A semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern, wherein the interconnect structure includes a graphene liner. The semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. The inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. The semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. The semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern.

A semiconductor device includes a semiconductor substrate, an integrated device ort the semiconductor substrate, a first redistribution layer on the semiconductor substrate, the first redistribution layer having first conductive patterns electrically connected to the integrated device, a second redistribution layer on the first redistribution layer, the second redistribution layer having second conductive patterns connected to the first conductive patterns, and third conductive patterns on a top surface of the second redistribution layer. The third conductive patterns include pads connected to the second conductive patterns, under-bump pads spaced apart from the pads, a grouping pattern between the pads and an outer edge of the second redistribution layer, and wiring lines that connect the under-bump pads to the pads and connect the pads to the grouping pattern.

A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.

The present application discloses a semiconductor device with two stress-relieving structures and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a first stress-relieving structure including a first conductive frame positioned above the semiconductor substrate and a plurality of first insulating pillars positioned within the conductive frame, a second stress-relieving structure including a plurality of second conductive pillars positioned above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars is positioned within the second insulating frame, and a conductive structure including a supporting portion positioned above the second stress-relieving structure, a conductive portion positioned adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion. The plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame.