A 3D semiconductor device, the device including: a first die including first transistors and first interconnect; and a second die including second transistors and second interconnect, where the first die is overlaid by the second die, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is pretested, where the second die includes an array of memory cells, where the first die includes control logic to control reads and writes to the array of memory cells, where the second die is bonded to the first die, and where the bonded includes hybrid bonding.

Semiconductor packages and methods of forming the same are disclosed. One of the methods includes the following steps. A first die is provided, wherein the first die comprises a first substrate, a first interconnect structure over the first substrate, and a first pad disposed over and electrically connected to the first interconnect structure. A first bonding dielectric layer is formed over the first die to cover the first die. By using a single damascene process, a first bonding via penetrating the first bonding dielectric layer is formed, to electrically connect the first interconnect structure.

The present disclosure relates to a method of manufacturing a first electronic circuit including a planar surface, intended to be affixed to a second electronic circuit by a self-assembly method with a hybrid molecular bonding, and first electrically-conductive pads exposed on the surface. The method includes the forming of a peripheral area around the surface including second exposed and raised pads, each at least partly having the same composition as the first pads.

Embodiments described herein relate to maintaining alignment between materials having different coefficients of thermal expansion during a bonding process of a light emitting diode (LED) device. The LED device includes a LED array and a backplane. The LED array and the blackplane each include a plurality of electrodes. During a bonding process where the electrodes of the LED array and electrodes of a backplane are bonded together, an alignment material having a coefficient of thermal expansion different than a coefficient of thermal expansion of the material of the LED array is deposited between LEDs of the LED array.

A semiconductor structure includes a first die and a plurality of first dummy pads. The first die includes a first interconnect structure and a first active pad electrically connected to the first interconnect structure. The first dummy pads laterally surround the first active pad and are electrically floating.

A manufacturing method for manufacturing a stacked substrate by bonding two substrates includes: acquiring information about crystal structures of a plurality of substrates; and determining a combination of two substrates to be bonded to each other, based on the information about the crystal structures. In the manufacturing method described above, the information about the crystal structures may include at least one of plane orientations of bonding surfaces and crystal orientations in a direction in parallel with the bonding surfaces. In the manufacturing methods described above, the determining may include determining a combination of the two substrates with a misalignment amount after bonding being equal to or smaller than a predetermined threshold.

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.

A pattern structure for a display device includes a substrate, a protrusion pattern on the substrate, a first conductive pattern covering an upper surface of the protrusion pattern, an interlayer insulating layer on the first conductive pattern and including a contact hole, and a second conductive pattern on the interlayer insulating layer and connected to the first conductive pattern. The contact hole overlaps the protrusion pattern and the first conductive pattern.

Semiconductor devices having interconnect structures with vertically offset bonding surfaces, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate at least partially covered by a first dielectric material having an upper surface, and an interconnect structure extending therefrom. The interconnect structure can include a plurality of conductive elements, and a continuous region of a first insulating material at least partially between the plurality of conductive elements. The plurality of conductive elements and the continuous region can have coplanar end surfaces. The interconnect structure can further include a perimeter structure at least partially surrounding the plurality of conductive elements and the continuous region. The perimeter structure can have an uppermost surface that can be vertically offset from the upper surface of the first dielectric material and/or the coplanar end surfaces.

A chip structure is provided. The chip structure includes a substrate, a redistribution layer over the substrate, a bonding pad over the redistribution layer, a shielding pad over the redistribution layer and surrounding the bonding pad, an insulating layer over the redistribution layer and the shielding pad, and a bump over the bonding pad and the insulating layer. The insulating layer includes a first part and a second part surrounded by the first part, the first part has first thickness, the second part has a second thickness, and the first thickness and the second thickness are different.