H01L2224/02255

ISOLATION STRUCTURE FOR BOND PAD STRUCTURE
20210043593 · 2021-02-11 ·

Various embodiments of the present disclosure are directed towards a semiconductor device structure including a bond pad isolation structure. A semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. A bond pad extends through the semiconductor substrate. The bond pad isolation structure is disposed within the semiconductor substrate. The bond pad isolation structure extends from the front-side surface to the back-side surface of the semiconductor substrate and continuously extends around the bond pad.

Semiconductor structure and manufacturing method thereof

A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure is on the dielectric surface. A conductive pad is on the dielectric surface and is leveled with the first protecting structure. A polymer layer is over the first protecting structure and the conductive pad. A conductive bump is electrically coupled to the conductive pad through an opening of the polymer layer. A method for manufacturing a semiconductor structure is also provided.

METAL LAYER PATTERNING FOR MINIMIZING MECHANICAL STRESS IN INTEGRATED CIRCUIT PACKAGES

A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
20210210447 · 2021-07-08 ·

A semiconductor structure is provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure over the dielectric surface. A first protecting structure over the passivation layer. A conductive pad over the dielectric surface. A polymer layer over the first protecting structure and the conductive pad. A conductive bump electrically coupled to the conductive pad through an opening of the polymer layer. A first portion of the first protecting structure is leveled with the conductive pad and a second portion of the first protecting structure is higher than the conductive pad.

Semiconductor device and method of manufacturing the same
11862586 · 2024-01-02 · ·

In one embodiment, a semiconductor device includes a first insulator, a first pad provided in the first insulator, a second insulator provided on the first insulator, and a second pad provided on the first pad in the second insulator. Furthermore, the first insulator includes a first film that is in contact with the first pad and the second insulator, and a second film provided at an interval from the first pad and the second insulator, and including a portion provided at a same height as at least a portion of the first pad.

METHOD FOR PREPARING DISPLAY SUBSTRATE AND DISPLAY SUBSTRATE
20240006421 · 2024-01-04 ·

Disclosed is a method for preparing a display substrate, including: providing a driving substrate; wherein the driving substrate includes: a base substrate; a pixel driving circuit layer; a first pad and a second pad, spaced from each other, and connected to the pixel driving circuit layer; and an electrostatic protection alignment, spaced from the first pad; and transferring a light-emitting element to the driving substrate, such that an anode of the light-emitting element is connected in alignment with the first pad and a cathode of the light emitting-element is connected in alignment with the second pad. The first pad includes a first toothed tip arranged on a side of the first pad facing the electrostatic protection alignment, and the electrostatic protection alignment includes a second toothed tip arranged on a side of the electrostatic protection alignment facing the first pad.

MICRO LED DISPLAY HAVING MULTI-COLOR PIXEL ARRAY AND METHOD OF FABRICATING THE SAME BASED ON INTEGRATION WITH DRIVING CIRCUIT THEREOF
20210005589 · 2021-01-07 ·

Disclosed is a micro LED display having a multi-color pixel array and a method of fabricating the same based on integration with a driving circuit thereof. According to various embodiments, the display may be fabricated by providing an IC device in which a driving circuit has been wired, forming, in one surface of the IC device, a plurality of pixels on which a plurality of partial pixels for emitting different color lights has been stacked, and electrically connecting the partial pixels to the driving circuit using connection members.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
20200381378 · 2020-12-03 ·

A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure is on the dielectric surface. A conductive pad is on the dielectric surface and is leveled with the first protecting structure. A polymer layer is over the first protecting structure and the conductive pad. A conductive bump is electrically coupled to the conductive pad through an opening of the polymer layer. A method for manufacturing a semiconductor structure is also provided.

Die-on-Interposer Assembly with Dam Structure and Method of Manufacturing the Same
20200373215 · 2020-11-26 ·

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

SEMICONDUCTOR PACKAGES WITH CRACK PREVENTING STRUCTURE

A semiconductor package includes a semiconductor substrate, an interconnect structure disposed over the substrate, a first passivation layer disposed over an interconnect structure, a contact pad disposed over the first passivation layer, a dummy disposed around the contact pad and over the first passivation layer, and a second passivation layer overlaying the dummy and the contact pad.