Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

A semiconductor package includes a power semiconductor chip comprising SiC, and a leadframe part including Cu. The power semiconductor chip is arranged on the leadframe part. A solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part includes at least one intermetallic phase.

A semiconductor package includes a power semiconductor chip comprising SiC, and a leadframe part including Cu. The power semiconductor chip is arranged on the leadframe part. A solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part includes at least one intermetallic phase.