A sintering powder comprising copper particles, wherein: the particles are at least partially coated with a capping agent, and the particles exhibit a D10 of greater than or equal to 100 nm and a D90 of less than or equal to 2000 nm.

A semiconductor device manufacturing method including preparing a semiconductor substrate including an electrode; forming a wire connected to the electrode; forming a first insulating film including a first opening that partially exposes the wire; forming a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; forming a solder film on a surface of the base portion; and fusing solder included in the solder film by a first heat treatment, and filling the recess with the fused solder.

A semiconductor device includes a bonding pad that includes a base portion having a base layer. A bond wire or clip is bonded to a bonding region of a main surface of the bonding pad. A supplemental structure is in direct contact with the base portion next to the bonding region. A specific heat capacity of the supplemental structure is higher than a specific heat capacity of the base layer.

A method of forming a solar cell device that includes forming a porous layer in a monocrystalline donor substrate and forming an epitaxial semiconductor layer on the porous layer. A solar cell structure is formed on the epitaxial semiconductor layer. A carrier substrate is bonded to the solar cell structure through a bonding layer. The monocrystalline donor substrate is removed by cleaving the porous layer. A grid of metal contacts is formed on the epitaxial semiconductor layer. The exposed portions of the epitaxial semiconductor layer are removed. The exposed surface of the solar cell structure is textured. The textured surface may be passivated, in which the passivated surface can provide an anti-reflective coating.

A method of forming a solar cell device that includes forming a porous layer in a monocrystalline donor substrate and forming an epitaxial semiconductor layer on the porous layer. A solar cell structure is formed on the epitaxial semiconductor layer. A carrier substrate is bonded to the solar cell structure through a bonding layer. The monocrystalline donor substrate is removed by cleaving the porous layer. A grid of metal contacts is formed on the epitaxial semiconductor layer. The exposed portions of the epitaxial semiconductor layer are removed. The exposed surface of the solar cell structure is textured. The textured surface may be passivated, in which the passivated surface can provide an anti-reflective coating.

A chip interconnection structure, a chip and a chip interconnection method. The chip interconnection structure includes a first chip and at least one second chip, where a transfer surface of the first chip and a transfer surface of the second chip are disposed oppositely, at least one conductive component is further provided between the second chip and the first chip, each conductive component includes at least one conductive member, and the conductive member is connected between a pad of the second chip and a pad of the first chip. The chip interconnection structure can allow two or more than two chips to be interconnected and to communicate at a high speed.

A chip interconnection structure, a chip and a chip interconnection method. The chip interconnection structure includes a first chip and at least one second chip, where a transfer surface of the first chip and a transfer surface of the second chip are disposed oppositely, at least one conductive component is further provided between the second chip and the first chip, each conductive component includes at least one conductive member, and the conductive member is connected between a pad of the second chip and a pad of the first chip. The chip interconnection structure can allow two or more than two chips to be interconnected and to communicate at a high speed.

A semiconductor device manufacturing method including preparing a semiconductor substrate including an electrode; forming a wire connected to the electrode; forming a first insulating film including a first opening that partially exposes the wire; forming a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; forming a solder film on a surface of the base portion; and fusing solder included in the solder film by a first heat treatment, and filling the recess with the fused solder.

A via for semiconductor devices is disclosed. Implementations of vias for semiconductor devices may include: a semiconductor substrate that includes a first side; a via extending from the first side of the semiconductor substrate to a pad; a polymer layer coupled along an entire sidewall of the via, the polymer layer in direct contact with the pad; and a metal layer directly coupled over the polymer layer and directly coupled with the pad.

A via for semiconductor devices is disclosed. Implementations of vias for semiconductor devices may include: a semiconductor substrate that includes a first side; a via extending from the first side of the semiconductor substrate to a pad; a polymer layer coupled along an entire sidewall of the via, the polymer layer in direct contact with the pad; and a metal layer directly coupled over the polymer layer and directly coupled with the pad.