Patent classifications
H01L2224/0332
Mechanically anchored C4 pad and method of forming same
The present disclosure relates generally to flip chip technology and more particularly, to a method for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure and a structure formed thereby. In an embodiment, a method is disclosed that includes forming a C4 pad on a patterned dielectric layer having grooves therein, the grooves providing an interfacial surface area between the patterned dielectric layer and the C4 pad sufficient to inhibit the C4 pad from delaminating during thermal expansion or contraction.
Multiple plated via arrays of different wire heights on a same substrate
Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component.
Multiple plated via arrays of different wire heights on a same substrate
Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component.
Solder ball application for singular die
A device is provided. The device includes one or more of a singular die, one of another die, a printed circuit board, and a substrate, and one or more solder balls. The singular die includes one or more reconditioned die pads, which include die pads of the singular die with a plurality of metallic layers applied. The other die, printed circuit board, and the substrate include one or more bond pads. The one or more solder balls are between the one or more reconditioned die pads and the one or more bond pads.
Solder ball application for singular die
A device is provided. The device includes one or more of a singular die, one of another die, a printed circuit board, and a substrate, and one or more solder balls. The singular die includes one or more reconditioned die pads, which include die pads of the singular die with a plurality of metallic layers applied. The other die, printed circuit board, and the substrate include one or more bond pads. The one or more solder balls are between the one or more reconditioned die pads and the one or more bond pads.
Methods and devices for fabricating and assembling printable semiconductor elements
The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
Methods and devices for fabricating and assembling printable semiconductor elements
The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
Semiconductor structure and manufacturing method thereof
A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor.
Semiconductor structure and manufacturing method thereof
A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor.
Methods for registration of circuit dies and electrical interconnects
A method includes placing an electronic device on a pliable mating surface on a major surface of a mold such that at least one contact pad on the electronic device presses against the pliable mating surface. The pliable mating surface is on a microstructure in an arrangement of microstructures on the major surface of the mold. A liquid encapsulant material is applied over the electronic device and the major surface of the mold, and then hardened to form a carrier for the electronic device. The mold and the carrier are separated such that the microstructures on the mold form a corresponding arrangement of microchannels in the carrier, and at least one contact pad on the electronic device is exposed in a microchannel in the arrangement of microchannels. A conductive particle-containing liquid is deposited in the microchannel, which directly contacts the contact pad exposed in the microchannel.