A power semiconductor contact structure for power semiconductor modules, which has at least one substrate 1 and a metal molded body 2 as an electrode, which are sintered one on top of the other by means of a substantially uninterrupted sintering layer 3a with regions of varying thickness. The metal molded body 2 takes the form here of a flexible contacting film 5 of such a thickness that this contacting film is sintered with its side 4 facing the sintering layer 3a onto the regions of varying thickness of the sintering layer substantially over the full surface area. A description is also given of a method for forming a power semiconductor contact structure in a power semiconductor module that has a substrate and a metal molded body. The forming of the power semiconductor contact structure is performed firstly by applying a layer of sintering material of locally varying thickness to either the metal molded body 2 or the substrate, followed by sintering together the contacting film 5 with the substrate 1 by using the properties of the layer of sintering material that are conducive to connection, the contacting film 5 being made to develop its distinct form to correspond to the varying thickness of the layer of sintering material 3a.

A method of making a semiconductor device comprising the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, and dicing the first KGU and KGD from the first redistribution interconnect structure. The method further includes the steps of testing a unit of the second redistribution interconnect structure to determine a second KGU of the second redistribution interconnect structure and disposing first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure.

In described examples, a first device on a first surface of a substrate is coupled to a structure arranged on a second surface of the substrate. In at least one example, a first conductor arranged on the first surface is coupled to circuitry of the first device. An elevated portion of the first conductor is supported by disposing an encapsulate and curing the encapsulate. The first conductor is severed by cutting the encapsulate and the first conductor. A second conductor is coupled to the first conductor. The second conductor is coupled to the structure arranged on the second surface of the substrate.

A method for assembling a packaged integrated circuit for operating reliably at elevated temperatures is provided. The method includes providing an extended bond pad over an original die pad of an extracted die to create a modified extracted die. The extracted die is a fully functional semiconductor die that has been removed from a finished packaged integrated circuit. The method also includes placing the modified extracted die into a cavity of a package base and bonding a new bond wire between the extended bond pad and a lead of the package base or a downbond, and sealing a package lid to the package base and the cavity of the package.

A method for assembling a packaged integrated circuit for operating reliably at elevated temperatures is provided. The method includes providing an extended bond pad over an original die pad of an extracted die to create a modified extracted die. The extracted die is a fully functional semiconductor die that has been removed from a finished packaged integrated circuit. The method also includes placing the modified extracted die into a cavity of a package base and bonding a new bond wire between the extended bond pad and a lead of the package base or a downbond, and sealing a package lid to the package base and the cavity of the package.

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

A method of making a semiconductor device comprising the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, and dicing the first KGU and KGD from the first redistribution interconnect structure. The method further includes the steps of testing a unit of the second redistribution interconnect structure to determine a second KGU of the second redistribution interconnect structure and disposing first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure.

Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.

Electronic device package technology is disclosed. In one example, an electronic device includes a plurality of dies stacked on a substrate and a reference die on the plurality of dies and having a fiducial marker that indicates a spatial position of the plurality of dies for alignment of an electronics assembly tool. The fiducial marker can comprise a physical alteration of the reference die, such as indicia that is sawed or laser/plasma/chemical etched. A transparent dielectric layer is disposed on the reference die such that the tool can locate the fiducial marker in three dimensional space through the transparent layer. The dielectric layer is etched corresponding to a photomask after a photoresist is disposed on the dielectric layer. The etched dielectric layer comprises at least one redistribution layer electrically coupled to the vertical wire interconnect structure to provide an ultra-thin package. A method of aligning an electronics assembly tool is disclosed.

A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.