During electro-oxidative metal removal on a semiconductor substrate, the substrate having a metal layer is anodically biased and the metal is electrochemically dissolved into an electrolyte. Metal particles (e.g., copper particles when the dissolved metal is copper) can inadvertently form on the surface of the substrate during electrochemical metal removal and cause defects during subsequent semiconductor processing. Contamination with such particles can be mitigated by preventing particle formation and/or by dissolution of particles. In one implementation, mitigation involves using an electrolyte that includes an oxidizer, such as hydrogen peroxide, during the electrochemical metal removal. An electrochemical metal removal apparatus in one embodiment has a conduit for introducing an oxidizer to the electrolyte and a sensor for monitoring the concentration of the oxidizer in the electrolyte.

During electro-oxidative metal removal on a semiconductor substrate, the substrate having a metal layer is anodically biased and the metal is electrochemically dissolved into an electrolyte. Metal particles (e.g., copper particles when the dissolved metal is copper) can inadvertently form on the surface of the substrate during electrochemical metal removal and cause defects during subsequent semiconductor processing. Contamination with such particles can be mitigated by preventing particle formation and/or by dissolution of particles. In one implementation, mitigation involves using an electrolyte that includes an oxidizer, such as hydrogen peroxide, during the electrochemical metal removal. An electrochemical metal removal apparatus in one embodiment has a conduit for introducing an oxidizer to the electrolyte and a sensor for monitoring the concentration of the oxidizer in the electrolyte.

A package structure includes the following: a logic die; and a plurality of core dies sequentially stacked on the logic die along a vertical direction, in which the plurality of core dies include a first core die and a second core die interconnected through a hybrid bonding member; the hybrid bonding member includes: a first contact pad located on a surface of the first core die; and a second contact pad located on a surface of the second core die; the first contact pad is in contact bonding with the second contact pad.

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.

A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

A method of fabricating an IC device is disclosed, in which a dielectric layer is first etched to form a contact opening and a dummy opening. Both do not extend through the dielectric layer, the contact opening has a width greater than that of the dummy opening. A sacrificial layer, which covers inner surface of the dummy opening and the dielectric layer at side surface of the contact opening, and from which the dielectric layer at bottom surface of the contact opening is exposed, is then formed, and under protection of this sacrificial layer, the dielectric layer exposed in the contact opening is etched in a self-aligned manner, a self-aligned contact hole is formed, in which a surface of the conductive structure is exposed. In this way, reliability of a contact that extends in both contact opening and self-aligned contact hole is ensured, avoiding the problem of possible contact failure.

A semiconductor package includes: a first semiconductor chip; a second semiconductor chip; and a bonding structure at an interface between the first and second semiconductor chips. The bonding structure includes: a first bonding insulating layer on the first semiconductor chip; a first connection pad in a first pad opening formed in the first bonding insulating layer, the first connection pad including a first pad layer, a first interface layer including a copper oxide, and a first capping layer; a second bonding insulating layer on the second semiconductor chip; and a second connection pad in a second pad opening formed in the second bonding insulating layer, the second connection pad including a second pad layer, a second interface layer including a copper oxide, and a second capping layer. The first and second capping layers include copper monocrystal layers having a (111) orientation.

A semiconductor package includes: a first semiconductor chip; a second semiconductor chip; and a bonding structure at an interface between the first and second semiconductor chips. The bonding structure includes: a first bonding insulating layer on the first semiconductor chip; a first connection pad in a first pad opening formed in the first bonding insulating layer, the first connection pad including a first pad layer, a first interface layer including a copper oxide, and a first capping layer; a second bonding insulating layer on the second semiconductor chip; and a second connection pad in a second pad opening formed in the second bonding insulating layer, the second connection pad including a second pad layer, a second interface layer including a copper oxide, and a second capping layer. The first and second capping layers include copper monocrystal layers having a (111) orientation.