A semiconductor structure, a method for forming a semiconductor structure, a stacked structure, and a wafer stacking method are provided. The semiconductor structure includes: a semiconductor substrate; a first dielectric layer on a surface of a semiconductor substrate; a top metal layer, in which the top metal layer is located in the first dielectric layer, and the top metal layer penetrates through the first dielectric layer; and a buffer layer located between the top metal layer and the first dielectric layer.

A microelectronic device has bump bonds and an inductor on a die. The microelectronic device includes first lateral conductors extending along a terminal surface of the die, wherein at least some of the first lateral conductors contact at least some of terminals of the die. The microelectronic device also includes conductive columns on the first lateral conductors, extending perpendicularly from the terminal surface, and second lateral conductors on the conductive columns, opposite from the first lateral conductors, extending laterally in a plane parallel to the terminal surface. A first set of the first lateral conductors, the conductive columns, and the second lateral conductors provide the bump bonds of the microelectronic device. A second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form the inductor. Methods of forming the microelectronic device are also disclosed.

Discussed generally herein are methods and devices including or providing a redistribution layer device without under ball metallization. A device can include a substrate, electrical interconnect circuitry in the substrate, redistribution layer (RDL) circuitry electrically connected to the electrical interconnect circuitry, a conductive bump electrically connected to the RDL circuitry, the conductive bump interfacing directly with the RDL circuitry, and a sheet molding material over the substrate.

Discussed generally herein are methods and devices including or providing a redistribution layer device without under ball metallization. A device can include a substrate, electrical interconnect circuitry in the substrate, redistribution layer (RDL) circuitry electrically connected to the electrical interconnect circuitry, a conductive bump electrically connected to the RDL circuitry, the conductive bump interfacing directly with the RDL circuitry, and a sheet molding material over the substrate.

A semiconductor structure and a method of manufacturing the semiconductor structure are provided. The semiconductor structure includes a substrate including a plurality of pads spaced apart from each other, a first groove, and a second groove connected with the first groove, the first and the second grooves located in the substrate. The first groove is located on the side of the second groove away from the plurality of pads, and the bottom of the second groove exposes a corresponding pad of the plurality of pads. The orthographic projection of the second groove on the substrate is located within the orthographic projection of the first groove on the substrate. A redistribution layer is disposed on a surface of the corresponding pad, the inner wall of the first groove, and the inner wall and the bottom of the second groove. The semiconductor structure prevents contamination or damage of test probes.

A display apparatus is disclosed that includes a substrate, a display element, a transistor, and a pad. The substrate includes a display area and a peripheral area. The display element is disposed on the display area. The transistor is electrically connected to the display element. The pad is disposed on the peripheral area and having a multilayered structure. The pad includes a pad metal layer, a first pad protective layer disposed on the pad metal layer, and a second pad protective layer interposed between the pad metal layer and the first pad protective layer. The second pad protective layer includes a different material from the first pad protective layer. The transistor includes a semiconductor layer disposed on the substrate, a gate electrode disposed on a gate insulating layer that covers the semiconductor layer, and a connection electrode arranged on an interlayer insulating layer covering the gate electrode. The connection electrode has the same multilayered structure as the multilayered structure of the pad, and the connection electrode is connected to the semiconductor layer.

In a semiconductor device, a first structure including a first uneven unit and a second structure covering the first structure and including a second uneven unit are formed in a bonding region defined in a semiconductor substrate. Metal wiring is joined to the second uneven unit in the second structure. A depth of a recess in the second uneven unit is shallower than a depth of a recess in the first uneven unit. An insulating member defining the bonding region is formed so as to reach the semiconductor substrate.

A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.

A tin plating solution and a method for fabricating a semiconductor device are provided. The tin plating solution comprises tin ions supplied from a soluble tin electrode, an aliphatic sulfonic acid having a carbon number of 1 to 10, an anti-oxidant, a wetting agent, and a grain refiner that is an aromatic carbonyl compound.

A tin plating solution and a method for fabricating a semiconductor device are provided. The tin plating solution comprises tin ions supplied from a soluble tin electrode, an aliphatic sulfonic acid having a carbon number of 1 to 10, an anti-oxidant, a wetting agent, and a grain refiner that is an aromatic carbonyl compound.