A semiconductor packaging structure includes a die including a bond pad and a first metal layer structure disposed on the die, the first metal layer structure having a first width, the first metal layer structure including a first metal layer, the first metal layer electrically coupled to the bond pad. The semiconductor packaging structure also includes a first photosensitive material around sides of the first metal layer structure and a second metal layer structure disposed over the first metal layer structure and over a portion of the first photosensitive material, the second metal layer structure electrically coupled to the first metal layer structure, the second metal layer structure having a second width, where the second width is greater than the first width. Additionally, the semiconductor packaging structure includes a second photosensitive material around sides of the second metal layer structure.

A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.

A semiconductor structure includes a semiconductor die containing an array of first bonding structures. Each of the first bonding structures includes a first metal pad located within a dielectric material layer and a basin-shaped underbump metallization (UBM) pad located within a respective opening in a passivation dielectric layer and contacting the first metal pad. An interposer includes an array of second bonding structures, wherein each of the second bonding structures includes an underbump metallization (UBM) pillar having a respective cylindrical shape. The semiconductor die is bonded to the interposer through an array of solder material portions that are bonded to a respective one of the first-type bonding structures and to a respective one of the second-type bonding structures.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

A method of fabricating an IC device is disclosed, in which a dielectric layer is first etched to form a contact opening and a dummy opening. Both do not extend through the dielectric layer, the contact opening has a width greater than that of the dummy opening. A sacrificial layer, which covers inner surface of the dummy opening and the dielectric layer at side surface of the contact opening, and from which the dielectric layer at bottom surface of the contact opening is exposed, is then formed, and under protection of this sacrificial layer, the dielectric layer exposed in the contact opening is etched in a self-aligned manner, a self-aligned contact hole is formed, in which a surface of the conductive structure is exposed. In this way, reliability of a contact that extends in both contact opening and self-aligned contact hole is ensured, avoiding the problem of possible contact failure.

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

A structure includes a controlled polyimide profile. A method for forming such a structure includes depositing, on a substrate, a photoresist containing polyimide and performing a first anneal at a first temperature. The method further includes exposing the photoresist to a radiation source through a photomask having a pattern associated with a shape of a polyimide opening. The method further includes performing a second anneal at a second temperature and removing a portion of the photoresist to form the polyimide opening. The method further includes performing a third anneal at a third temperature and cleaning the polyimide opening by ashing.

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.