There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h.sub.1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h.sub.2 of the solder layer is measured from the upper surface of the resist layer. Thickness h.sub.1 is greater than or equal to a half of thickness h.sub.2 and is smaller than or equal to thickness h.sub.2.

A chip package is provided. The chip package includes a first substrate and a second substrate disposed over the first substrate. The first substrate and the second substrate have a lower surface and an upper surface, and the second substrate includes a first recess region surrounding the second substrate. The first recess region has a tapered sidewall and a bottom surface that is between the lower and upper surfaces of the second substrate. The chip package also includes at least one conductive pad disposed on the upper surface of the second substrate and a redistribution layer (RDL) correspondingly disposed on the conductive pad. The RDL is extended from the conductive pad onto the bottom surface of the first recess region along the tapered sidewall of the first recess region. A method of forming a chip package is also provided.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

In examples, a semiconductor package comprises a bond pad surface layer, a second conductive layer positioned below the bond pad surface layer, and a perforated plate positioned between and abutting the bond pad surface layer and the second conductive layer. The perforated plate has a monolithic conductive member and multiple insulation members embedded within the conductive member, the insulation members having thicknesses approximately equivalent to that of the conductive member. The package also includes a semiconductor substrate including a circuit, the semiconductor substrate positioned below the second conductive layer.

Provided is a three-dimensional integrated circuit (3DIC) structure including a first die and a second die bonded together by a hybrid bonding structure. One of the first die and the second die has a pad and a cap layer disposed over the pad. The cap layer exposes a portion of a top surface of the pad, and the portion of the top surface of the pad has a probe mark. A bonding metal layer of the hybrid bonding structure penetrates the cap layer to electrically connect to the pad. A method of fabricating the first die or the second die of 3DIC structure is also provided.

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

In some embodiments, an integrated chip (IC) is provided. The IC includes a metallization structure disposed over a semiconductor substrate, where the metallization structure includes an interconnect structure disposed in an interlayer dielectric (ILD) structure. A passivation layer is disposed over the metallization structure, where an upper surface of the interconnect structure is at least partially disposed between opposite inner sidewalls of the passivation layer. A sidewall spacer is disposed along the opposite inner sidewalls of the passivation layer, where the sidewall spacer has rounded sidewalls. A conductive structure is disposed on the passivation layer, the rounded sidewalls of the sidewall spacer, and the upper surface of the interconnect structure.

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

An LED chip provided by an embodiment includes a first semiconductor layer; an active layer and a second semiconductor layer located sequentially on the first semiconductor layer. A first contact electrode extends through the active layer and the second semiconductor layer and is electrically connected to the first semiconductor layer; a second contact electrode is located on the second semiconductor layer and is electrically connected to the second semiconductor layer; a first extension electrode is located on the first contact electrode and is electrically connected to the first contact electrode, the first extension electrode comprises a plurality of concave spots for soldering; and a second extension electrode is located on the second contact electrode, electrically connected to the second contact electrode and isolated from the first extension electrode, and the second extension electrode includes a plurality of concave spots for soldering.

An LED chip provided by an embodiment includes a first semiconductor layer; an active layer and a second semiconductor layer located sequentially on the first semiconductor layer. A first contact electrode extends through the active layer and the second semiconductor layer and is electrically connected to the first semiconductor layer; a second contact electrode is located on the second semiconductor layer and is electrically connected to the second semiconductor layer; a first extension electrode is located on the first contact electrode and is electrically connected to the first contact electrode, the first extension electrode comprises a plurality of concave spots for soldering; and a second extension electrode is located on the second contact electrode, electrically connected to the second contact electrode and isolated from the first extension electrode, and the second extension electrode includes a plurality of concave spots for soldering.