A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

A plasma-based ashing process for surface conditioning and material modification to improve bond pad metallurgical properties as well as semiconductor device performance. Residue materials generated in a removal process at a process layer having recessed features with Ni—Pd surfaces are ashed in a plasma reactor to reduce defect count and improve surface conditioning associated with bond pads of the semiconductor device.

Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.

Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.

Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device under thermal stress and the assembly performance of the semiconductor device in manufacturing steps. The method includes the following: forming a first electrode by depositing a first conductive film onto one main surface of a semiconductor substrate and patterning the first conductive film; forming a first metal film corresponding to a pattern of the first electrode onto the first electrode; forming a second electrode by depositing a second conductive film onto the other main surface of the semiconductor substrate; forming a second metal film thinner than the first metal film onto the second electrode; and collectively forming a third metal film onto each of the first metal film and the second metal film by electroless plating.

Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

A method of forming a package assembly includes forming a no-flow underfill layer on a substrate. The method further includes attaching a semiconductor die to the substrate. The semiconductor die comprises a bump and a molding compound layer in physical contact with a lower portion of the bump. An upper portion of the bump is in physical contact with the no-flow underfill layer.

A method of forming a package assembly includes forming a no-flow underfill layer on a substrate. The method further includes attaching a semiconductor die to the substrate. The semiconductor die comprises a bump and a molding compound layer in physical contact with a lower portion of the bump. An upper portion of the bump is in physical contact with the no-flow underfill layer.