A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact area of a gate clip is smaller than an area of a gate copper surface. The area of the contact area of the gate clip is larger than a gate aluminum surface. In another example, an area of a contact area of a gate pin is larger than an area of a gate copper surface. The area of the contact area of the gate pin is larger than a gate aluminum surface.

A semiconductor structure including an integrated circuit die and conductive bumps is provided. The integrated circuit die includes bump pads. The conductive bumps are disposed on the bump pads. Each of the conductive bumps includes a first pillar portion disposed on one of the bump pads and a second pillar portion disposed on the first pillar portion. The second pillar portion is electrically connected to one of the bump pads through the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. A package structure including the above-mentioned semiconductor structure is also provided.

A bumped solder pad and methods for adding bumps to a solder pad are provided. A substrate is provided having metal layer formed thereon and a solder pad formed from a portion of the metal layer. A surface treatment is applied to the solder pad. The surface treatment is patterned. The surface treatment is etched to produce at least one bump on the solder pad.

The present invention provides a resin composition having a high sensitivity and serving to produce a cured film with a low water absorption rate. The resin composition includes: (a) an alkali-soluble resin and (b1) an amido-phenol compound containing a phenolic hydroxyl group in which a monovalent group as represented by the undermentioned general formula (1) is located at the ortho position and/or (b2) an aromatic amido acid compound containing a carboxy group in which a monovalent group as represented by the undermentioned general formula (2) is located at the ortho position: ##STR00001##
wherein in general formula (1), X is a monovalent organic group having an alkyl group that contains 2 to 20 carbon atoms and bonds directly to the carbonyl carbon in general formula (1) or a monovalent organic group that has —(YO).sub.n—; and in general formula (2), U is a monovalent organic group that has an alkyl group containing 2 to 20 carbon atoms and bonding directly to the amide nitrogen in general formula (2) or a monovalent organic group that has —(YO).sub.n—; wherein Y is an alkylene group containing 1 to 10 carbon atoms and n is an integer of 1 to 20.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.

In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns.sup.2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.

An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.

The present invention is a resin composition including (a) a resin, (b) an antioxidizing agent, and (d) a crosslinking agent, wherein the resin composition is characterized by the following: the resin (a) is formed of one or more kinds of resins selected from among polyimide precursor, polyamide, polyimide, polybenzoxazole, and copolymers thereof; and the crosslinking agent (d) includes a phenolic hydroxyl group in one molecule, and also includes a substituent group having a molecular weight of 40 or more at both ortho positions of the phenolic hydroxyl group. Provided is the resin composition by which obtained is a pattern-cured film that enables fine patterns to be obtained, that exhibits excellent in-plane pattern uniformity while being curable at a low temperature of 250° C. or less, and that retains high extensibility and high adhesion with metal wires even after a reliability evaluation which is an actual-use accelerated test.

A semiconductor structure including an integrated circuit die and conductive bumps is provided. The integrated circuit die includes bump pads. The conductive bumps are disposed on the bump pads. Each of the conductive bumps includes a first pillar portion disposed on one of the bump pads and a second pillar portion disposed on the first pillar portion. The second pillar portion is electrically connected to one of the bump pads through the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. A package structure including the above-mentioned semiconductor structure is also provided.