Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

A method of manufacturing a semiconductor device is provided. The method includes forming a non-conductive layer over an active side of a semiconductor die partially encapsulated with an encapsulant. An opening in the non-conductive layer is formed exposing a portion of a bond pad of the semiconductor die. A laser ablated trench is formed at a surface of the non-conductive layer proximate to a perimeter of the opening. A bottom surface of the laser ablated trench is substantially roughened. An under-bump metallization (UBM) structure is formed over the bond pad and laser ablated trench.

In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

Provided here are: an electrically-conductive semiconductor substrate with which a semiconductor circuit is formed; an insulating film deposited on a major surface of the electrically-conductive semi-conductor substrate; and a bonding pad having fixing parts fixed onto the insulating film, side wall parts rising up from the fixing parts, and an electrode part connected to the side wall parts and disposed in parallel to the major surface; wherein the electrode part forms, together with the insulating film, a gap region therebetween, and portions of the electrode part where it is connected to the side wall parts are configured to have at least one of: a positional relationship in which they sandwich therebetween a central portion of the electrode part in its bonding region to be bonded to a bonding wire; and a positional relationship in which they surround the central portion.

Embodiments described herein provide techniques for forming an interconnect structure that includes micro features formed therein. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a metal pad over a substrate (e.g., a semiconductor package, a PCB, an interposer, etc.). Micro features may be formed in an edge of the metal pad or away from the edge of the metal pad. The micro features can assist with: (i) increasing the contact area between solder used to form an interconnect joint and the metal pad; and (ii) improving adherence of solder used to form an interconnect joint to the metal pad. These benefits can improve interconnect joint reliability by, among others, improving the interconnect joint's ability to absorb stress from substrates having differing coefficients of thermal expansion.

Embodiments described herein provide techniques for forming an interconnect structure that includes a bowl shaped pad. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a substrate (e.g., a semiconductor package, a PCB, etc.); and a metal pad over the substrate. The metal pad has a center region and an edge region. A thickness of the center region is smaller than a thickness of the edge region. A thickness of the center region may be non-uniform. The center region may have a bowl shape characterized by a stepped profile. The stepped profile is formed from metal layers arranged as steps. Alternatively, or additionally, the center region may have a bowl shape characterized by a curved profile. A pattern may be formed on or in a surface of the metal pad.