Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is provided. The method includes the following operations. In a first semiconductor structure, a first bonding layer is formed having a first dielectric layer and a plurality of protruding contact structures. In a second semiconductor structure, a second bonding layer is formed having a second dielectric layer and a plurality of recess contact structures. The plurality of protruding contact structures are bonded with the plurality of recess contact structures such that each of the plurality of protruding contacts is in contact with a respective recess contact structure.

Disclosed herein is a method that includes forming a contact plug to be embedded in a first insulating film formed on a semiconductor substrate; forming a probe pad on the first insulating film to contact with the contact plug; performing a test operation by probing the probe pad; removing the probe pad; forming a second insulating film to cover the contact plug after removing the probe pad; and forming a pad electrode to be embedded in the second insulating film.

A semiconductor device is provided that includes a bond pad, an insulating layer, and a bonding structure. The bond pad is in a dielectric layer and the insulating layer is over the bond pad; the insulating layer having an opening over the bond pad formed therein. The bonding structure electrically couples the bond pad in the opening. The bonding structure has a height that at least extends to an upper surface of the insulating layer.

A semiconductor device includes a first semiconductor die package. The first semiconductor package includes a molding compound, and a conductive element in the molding compound, wherein a top surface of the conductive element is above or co-planar with a top-most surface of the molding compound. The semiconductor device further includes a second semiconductor die package. The second semiconductor package includes a plurality of copper-containing contacts on a single metal pad, wherein each of the plurality of copper-containing contacts is bonded to the conductive element.

The semiconductor device according to the present invention comprises; a semiconductor element having one surface with a plurality of electrode pads; an electrode structure including a plurality of metal terminals and a sealing resin. The plurality of metal terminals being disposed in a region along a circumference of the one surface. The sealing resin holding the plurality of metal terminals and being disposed on the one surface of the semiconductor element. The electrode structure includes a first surface opposed to the one surface of the semiconductor element, a second surface positioned in an opposite side of the first surface, and a third surface positioned between the first surface and the second surface. Each of the plurality of metal terminals is exposed from the sealing resin in at least a part of the second surface and at least a part of the third surface.

There is provided a method for manufacturing a semiconductor device comprising: forming a first organic insulating layer on a semiconductor region; forming a bump base film including an edge portion contacting with the first organic insulating layer; performing heat treatment of the bump base film; and forming a second organic insulating layer so as to cover the edge portion of the bump base film and the first organic insulating layer around the bump base film while contacting with the first organic insulating layer, the second organic insulating layer being provided with a first opening that exposes a surface of the bump base film.

A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.

The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.

The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.

Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.