A chip package which includes a chip, at least one first dielectric layer, at least one second dielectric layer, at least one conductive circuit, and at least one third dielectric layer is provide. The conductive circuit is formed by highly concentrated silver paste or copper paste filled in at least one first groove of the first dielectric layer and at least one second groove of the second dielectric layer while at least one die pad of the chip is electrically connected with the conductive circuit for improving electrical conduction efficiency of the conductive circuit. Moreover, at least one die-pad bump is formed in the first groove, arranged at and electrically connected with a surface of the die pad for protecting of the die pad.

A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.

The present disclosure is directed to a method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The method includes the steps of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.

The present disclosure is directed to a method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The method includes the steps of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.

A semiconductor device includes a silicon layer, a metal silicide layer arranged directly on the silicon layer, and a solder layer arranged directly on the metal silicide layer.

A bonding structure and a method for manufacturing the bonding structure are provided. Multiple chips arranged in an array are formed on a surface of a wafer. Each of the chips includes a device structure, an interconnect structure electrically connected to the device structure, and a first package pad layer electrically connected to the interconnect structure. The first package pad layer is arranged at an edge region of the chip. A chip stack is obtained after bonding and cutting the multiple wafers, and the first package pad layer at the edge region of the chip is exposed.

The present disclosure is directed to method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique. The method includes operations of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.

The present disclosure is directed to method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique. The method includes operations of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.

Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.