A semiconductor device manufacturing method includes a preparation step and a sinter bonding step. In the preparation step, a sinter-bonding work having a multilayer structure including a substrate, semiconductor chips, and sinter-bonding material layers is prepared. The semiconductor chips are disposed on, and will bond to, one side of the substrate. Each sinter-bonding material layer contains sinterable particles and is disposed between each semiconductor chip and the substrate. In the sinter bonding step, a cushioning sheet having a thickness of 5 to 5000 μm and a tensile elastic modulus of 2 to 150 MPa is placed on the sinter-bonding work, the resulting stack is held between a pair of pressing faces, and, in this state, the sinter-bonding work between the pressing faces undergoes a heating process while being pressurized in its lamination direction, to form a sintered layer from each sinter-bonding material layer.

A semiconductor device manufacturing method includes a preparation step and a sinter bonding step. In the preparation step, a sinter-bonding work having a multilayer structure including a substrate, semiconductor chips, and sinter-bonding material layers is prepared. The semiconductor chips are disposed on, and will bond to, one side of the substrate. Each sinter-bonding material layer contains sinterable particles and is disposed between each semiconductor chip and the substrate. In the sinter bonding step, a cushioning sheet having a thickness of 5 to 5000 μm and a tensile elastic modulus of 2 to 150 MPa is placed on the sinter-bonding work, the resulting stack is held between a pair of pressing faces, and, in this state, the sinter-bonding work between the pressing faces undergoes a heating process while being pressurized in its lamination direction, to form a sintered layer from each sinter-bonding material layer.

A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ≥50 W/mK.

A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ≥50 W/mK.

An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.

A semiconductor device includes a chip body; a passivation layer on the chip body; a lower dielectric layer on the passivation layer; a first re-distribution pad on the lower dielectric layer; an upper dielectric layer on the lower dielectric layer, the upper dielectric layer having a groove that exposes an upper surface of the first re-distribution pad; and a second re-distribution pad on the upper dielectric layer. An upper surface of the second re-distribution pad is positioned at a higher level than the upper surface of the first re-distribution pad.

Integrated circuit IC package with one or more IC dies including solder features that are thermally coupled to the IC. The thermally coupled solder features (e.g., bumps) may be electrically insulated from solder features electrically coupled to the IC, but interconnected with each other by one or more metallization layers within a plane of the IC package. An in-plane interconnected network of thermal solder features may improve lateral heat transfer, for example spreading heat from one or more hotspots on the IC die. An under-bump metallization (UBM) may interconnect two or more thermal solder features. A through-substrate via (TSV) metallization may interconnect two or more thermal solder features. A stack of IC dies may include thermal solder features interconnected by metallization within one or more planes of the stack.

Integrated circuit IC package with one or more IC dies including solder features that are thermally coupled to the IC. The thermally coupled solder features (e.g., bumps) may be electrically insulated from solder features electrically coupled to the IC, but interconnected with each other by one or more metallization layers within a plane of the IC package. An in-plane interconnected network of thermal solder features may improve lateral heat transfer, for example spreading heat from one or more hotspots on the IC die. An under-bump metallization (UBM) may interconnect two or more thermal solder features. A through-substrate via (TSV) metallization may interconnect two or more thermal solder features. A stack of IC dies may include thermal solder features interconnected by metallization within one or more planes of the stack.

Flexible devices including conductive traces with enhanced stretchability, and methods of making and using the same are provided. The circuit die is disposed on a flexible substrate. Electrically conductive traces are formed in channels on the flexible substrate to electrically contact with contact pads of the circuit die. A first polymer liquid flows in the channels to cover a free surface of the traces. The circuit die can also be surrounded by a curing product of a second polymer liquid.

Flexible devices including conductive traces with enhanced stretchability, and methods of making and using the same are provided. The circuit die is disposed on a flexible substrate. Electrically conductive traces are formed in channels on the flexible substrate to electrically contact with contact pads of the circuit die. A first polymer liquid flows in the channels to cover a free surface of the traces. The circuit die can also be surrounded by a curing product of a second polymer liquid.