A bump structure includes a first bump disposed on a substrate, the first bump including a first metal, at least one antioxidant member surrounded by the first bump, the at least one antioxidant member including a second metal having an ionization tendency greater than an ionization tendency of the first metal, and a second bump disposed on the first bump and the at least one antioxidant member.

A bump structure includes a first bump disposed on a substrate, the first bump including a first metal, at least one antioxidant member surrounded by the first bump, the at least one antioxidant member including a second metal having an ionization tendency greater than an ionization tendency of the first metal, and a second bump disposed on the first bump and the at least one antioxidant member.

A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.

A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.

The semiconductor package has a metal layer, a first dielectric layer formed on a metal layer, and an opening formed through the first dielectric layer to expose a part of the metal layer. The bump structure has an under bump metallurgy (hereinafter UBM), a first buffer layer and a metal bump. The UBM is formed on the first part of the metal layer, a sidewall of the opening and a top surface of the first dielectric layer. The first buffer layer is formed between a part of the UBM corresponding to the top surface of the first dielectric layer and the top surface of the first dielectric layer. The metal bump is formed on the UBM. Therefore, the first buffer layer effectively absorbs a thermal stress to avoid cracks generated in the bump structure after the bonding step.

The semiconductor package has a metal layer, a first dielectric layer formed on a metal layer, and an opening formed through the first dielectric layer to expose a part of the metal layer. The bump structure has an under bump metallurgy (hereinafter UBM), a first buffer layer and a metal bump. The UBM is formed on the first part of the metal layer, a sidewall of the opening and a top surface of the first dielectric layer. The first buffer layer is formed between a part of the UBM corresponding to the top surface of the first dielectric layer and the top surface of the first dielectric layer. The metal bump is formed on the UBM. Therefore, the first buffer layer effectively absorbs a thermal stress to avoid cracks generated in the bump structure after the bonding step.

There is provided a semiconductor chip having four sides and being substantially formed in a rectangle, the semiconductor chip including: a first terminal which is located along one side of the four sides of the semiconductor chip and which is to be electrically connected to a solar cell outside the semiconductor chip; a second terminal which is located along the one side of the semiconductor chip and which is to be electrically connected to a secondary cell outside the semiconductor chip; and an interconnection line that electrically interconnects the first terminal and the second terminal.

There is provided a semiconductor chip having four sides and being substantially formed in a rectangle, the semiconductor chip including: a first terminal which is located along one side of the four sides of the semiconductor chip and which is to be electrically connected to a solar cell outside the semiconductor chip; a second terminal which is located along the one side of the semiconductor chip and which is to be electrically connected to a secondary cell outside the semiconductor chip; and an interconnection line that electrically interconnects the first terminal and the second terminal.

The invention relates to a paste, preferably for joining components of power electronics modules, the paste comprising a solder powder, a metal powder and a binder, wherein the binder binds solder powder and metal powder before a first heating. According to the invention, the binder is free of flux or is a flux having only low activation. In this way, a joining layer which exhibits only few included voids and good mechanical and electrical stability can be provided between a first and a second component.

The invention relates to a paste, preferably for joining components of power electronics modules, the paste comprising a solder powder, a metal powder and a binder, wherein the binder binds solder powder and metal powder before a first heating. According to the invention, the binder is free of flux or is a flux having only low activation. In this way, a joining layer which exhibits only few included voids and good mechanical and electrical stability can be provided between a first and a second component.