Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.

Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.

The present disclosure discloses a semiconductor device structure with an air gap for reducing capacitive coupling and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive pad over a first semiconductor substrate, and a first conductive structure over the first conductive pad. The semiconductor device structure also includes a second conductive structure over the first conductive structure, and a second conductive pad over the second conductive structure. The second conductive pad is electrically connected to the first conductive pad through the first and the second conductive structures. The semiconductor device structure further includes a second semiconductor substrate over the second conductive pad, a first passivation layer between the first and the second semiconductor substrates and covering the first conductive structure, and a second passivation layer between the first passivation layer and the second semiconductor substrate. The first and the second passivation layers surround the second conductive structure, and a first air gap is enclosed by the first and the second passivation layers.

The present disclosure discloses a semiconductor device structure with an air gap for reducing capacitive coupling and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive pad over a first semiconductor substrate, and a first conductive structure over the first conductive pad. The semiconductor device structure also includes a second conductive structure over the first conductive structure, and a second conductive pad over the second conductive structure. The second conductive pad is electrically connected to the first conductive pad through the first and the second conductive structures. The semiconductor device structure further includes a second semiconductor substrate over the second conductive pad, a first passivation layer between the first and the second semiconductor substrates and covering the first conductive structure, and a second passivation layer between the first passivation layer and the second semiconductor substrate. The first and the second passivation layers surround the second conductive structure, and a first air gap is enclosed by the first and the second passivation layers.

A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.

Peeling of a bonding material is prevented at a bonding portion between a base plate and an insulating substrate due to thermal stress to obtain a semiconductor device with improved reliability. The semiconductor device includes: a base plate; an insulating substrate including an insulating layer and is provided with metal layers on an upper surface and a lower surface of the insulating layer; a bonding material that bonds an upper surface of the base plate and a lower surface of the metal layer on a lower surface-side of the insulating layer; a case member that is disposed on the upper surface of the base plate to surround the insulating substrate; and a pressing member that is disposed in a region surrounded by the base plate and the case member, and is in contact with the upper surface of the insulating substrate while straddling facing sides of the insulating substrate.

A semiconductor device includes a semiconductor substrate, a gate insulator provided on a surface of the semiconductor substrate, a bonding film, including silicon or aluminum, provided on the gate insulator, and a gate pad layer provided above the bonding film, wherein the gate pad layer includes titanium in at least a region in contact with the bonding film.

A terminal connection portion, which includes an IC including a plurality of input bumps and a plurality of output bumps, and a terminal connection portion including a plurality of input terminal electrodes and a plurality of output terminal electrodes, is provided in a frame region, and in the terminal connection portion, an electrode insulating film is provided on the input terminal electrodes and the output terminal electrodes. A protruding portion is provided on the electrode insulating film, and the protruding portion overlaps with the IC in a plan view, and overlaps with the input bumps and the output bumps when viewed from a direction parallel to a substrate surface of a resin substrate layer.

A terminal connection portion, which includes an IC including a plurality of input bumps and a plurality of output bumps, and a terminal connection portion including a plurality of input terminal electrodes and a plurality of output terminal electrodes, is provided in a frame region, and in the terminal connection portion, an electrode insulating film is provided on the input terminal electrodes and the output terminal electrodes. A protruding portion is provided on the electrode insulating film, and the protruding portion overlaps with the IC in a plan view, and overlaps with the input bumps and the output bumps when viewed from a direction parallel to a substrate surface of a resin substrate layer.

The semiconductor package has a metal layer, a first dielectric layer formed on a metal layer, and an opening formed through the first dielectric layer to expose a part of the metal layer. The bump structure has an under bump metallurgy (hereinafter UBM), a first buffer layer and a metal bump. The UBM is formed on the first part of the metal layer, a sidewall of the opening and a top surface of the first dielectric layer. The first buffer layer is formed between a part of the UBM corresponding to the top surface of the first dielectric layer and the top surface of the first dielectric layer. The metal bump is formed on the UBM. Therefore, the first buffer layer effectively absorbs a thermal stress to avoid cracks generated in the bump structure after the bonding step.