An electronic device has a conductive shield between first and second regions in a multilevel metallization structure, as well as a capacitor with first and second terminals in the first region, the first terminal laterally overlaps the second terminal by an overlap distance of 1.0 μm to 6.0 μm, the conductive shield includes a first metal line that encircles the first terminal, and the first metal line is spaced apart from the first terminal by a gap distance of 0.5 μm to 1.0 μm.

A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.

A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.

A multi-die apparatus includes a plurality of die groups. Each die group includes a plurality of dies stacked parallel to each other and with an edge surface of each die aligned with a planar side surface. The multi-die apparatus also includes a base substrate structure that has a planar top surface characterized by a given direction of lattice crystalline planes. Each of the plurality of die groups is disposed sideways on the base substrate structure, with the planar side surface of each die group bonded to the planar top surface of the base substrate structure. One or more of the plurality of die groups are arranged in a non-parallel manner relative to the given direction of lattice crystalline planes of the base substrate structure.

A multi-die apparatus includes a plurality of die groups. Each die group includes a plurality of dies stacked parallel to each other and with an edge surface of each die aligned with a planar side surface. The multi-die apparatus also includes a base substrate structure that has a planar top surface characterized by a given direction of lattice crystalline planes. Each of the plurality of die groups is disposed sideways on the base substrate structure, with the planar side surface of each die group bonded to the planar top surface of the base substrate structure. One or more of the plurality of die groups are arranged in a non-parallel manner relative to the given direction of lattice crystalline planes of the base substrate structure.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a die attach film (DAF), at the first surface of the first die, including through-DAF vias (TDVs), wherein respective ones of the TDVs are electrically coupled to respective ones of the first conductive contacts; a conductive pillar in the first layer; and a second die, in a second layer on the first layer, wherein the second die is electrically coupled to the second conductive contacts on the second surface of the first die and electrically coupled to the conductive pillar.

A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.

A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.

Method and arrangement for assembling one or more microchips (415; 615; 715; 815; 915; 1015) into one or more holes (422; 722), respectively, in a substrate surface (421; 721) of a separate receiving substrate (420; 720; 820; 1020). The holes (422; 722) of the substrate is for microchip insertion out-of-plane in relation to said substrate surface. Each of said microchips is provided with a ferromagnetic layer (213; 613) of ferromagnetic material. The microchips are placed (503) on said substrate surface (421; 721) and it is applied and moved (504) one or more magnetic fields affecting said ferromagnetic layer (213; 613) of each microchip such that the microchips thereby become out-of-plane oriented in relation to said substrate surface (421; 721) and move over the substrate surface (421; 721) until assembled into said holes (422; 722).

An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.