A wiring (3) comprising electrical conductors (4, 5, 6, 7) is formed in a dielectric layer (2) on or above a semiconductor substrate (1), an opening is formed in the dielectric layer to uncover a contact pad (8), which is formed by one of the conductors, and a further opening is formed in the dielectric layer to uncover an area of a further conductor (5), separate from the contact pad. The further opening is filled with an electrically conductive material (9), and the dielectric layer is thinned from a side opposite the substrate, so that the electrically conductive material protrudes from the dielectric layer.

Disclosed are multi-junction light emitting diode (LED) formed by using eutectic bonding and method of manufacturing the multi-junction LED. The multi-junction LED is formed by stacking a separately formed light emitting structure on another light emitting structure by using eutectic bonding. Since separately grown light emitting structure is stacked on the light emitting structure using the eutectic metal alloy bonding, it is possible to prevent crystal defects occurring between the light emitting structures when sequentially grown. Further, since the eutectic metal alloy can be formed in various patterns, it is possible to control and optimize adhesive strength, transmittance of the light generated in the upper light emitting structure, and resistance.

A semiconductor device with reduced device resistance is disclosed. The semiconductor device comprises a semiconductor chip in which the chip thickness at the center portion of the chip where the circuit elements are disposed is uniform and is different from the chip thickness near the chip sides distant from the circuit elements.

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate having a first pad and a second pad thereon. A logic die is mounted on the substrate. The logic die includes a first logic die pad coupled to the first pad. A memory die is mounted on the substrate. The memory die includes a first memory die pad. A first redistribution layer (RDL) trace has a first terminal and a second terminal. The first terminal is coupled to the first pad through the first memory die pad. The second terminal is coupled to the second pad rather than the first pad.

A method of forming a semiconductor structure includes: forming an interconnect structure over a substrate; forming a pad over the interconnect structure, wherein the pad is electrically connected to the interconnect structure; forming a bonding dielectric layer over the interconnect structure; and forming a bonding metal layer in the bonding dielectric layer to electrically connect to the interconnect structure, wherein the bonding metal layer includes a via plug and a metal feature formed over the via plug, a height of the metal feature is greater than or equal to a height of the via plug.

The semiconductor device includes a supporting member, a conductive member, and a semiconductor element. The supporting member has a supporting surface facing in a thickness direction. The conductive member has an obverse surface facing the same side as the supporting surface faces in the thickness direction, and a reverse surface opposite to the obverse surface. The conductive member is bonded to the supporting member such that the reverse surface faces the supporting surface. The semiconductor element is bonded to the obverse surface. The semiconductor device further includes a first metal layer and a second metal layer. The first metal layer covers at least a part of the supporting surface. The second metal layer covers the reverse surface. The first metal layer and the second layer are bonded to each other by solid phase diffusion.

Reliability of a semiconductor device is improved. In the semiconductor device SA1, a snubber capacitor pad SNP electrically connected to the capacitor electrode of the snubber capacitor is formed on the surface of the semiconductor chip CHP.

A technique capable of improving a performance of a semiconductor detector is provided. The semiconductor detector is made based on injection of an underfill into a gap between a first semiconductor chip and a second semiconductor chip in a flip-chip connection state, but the underfill is not formed in periphery of a connection structure connecting a reading electrode pad and a gate terminal through a bump electrode.

To provide a semiconductor apparatus that makes it possible to further improve the efficiency in heat dissipation, and to provide an electronic apparatus that includes the semiconductor apparatus. A semiconductor apparatus is provided that includes a substrate, a plurality of chips each stacked on the substrate, and a plurality of guard rings each formed on an outer peripheral portion of a corresponding one of the plurality of chips to surround the corresponding one of the plurality of chips, in which at least portions of at least two of the plurality of guard rings are connected to each other through a thermally conductive material. Further, an electric apparatus is provided that includes the semiconductor apparatus.

A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first semiconductor device, a second semiconductor device, and an alignment material. The first semiconductor device has a first bonding layer, and the first bonding layer includes a first bond pad contacting an organic dielectric material. The second semiconductor device has a second bonding layer, and the second bonding layer includes a second bond pad contacting the organic dielectric material. The alignment material is between the first bonding layer and the second bonding layer.