Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.

A method for manufacturing an electronic circuit component includes: providing a first electronic component with one or several electrically conductive first contacts and with one or several insulating first supporting elements; providing a second electronic component with one or several electrically conductive second contacts and with one or several insulating second supporting elements; configuring a connecting structure with an interposer substrate, with electrically conductive third contacts, with one or several electrically conductive fourth contacts, with one or several insulating third supporting elements, with one or several electrically conductive fifth contacts, and with one or several insulating fourth supporting elements; connecting the first electronic component and the second electronic component to the connecting structure, wherein the first contacts are electrically connected to the fourth contacts, wherein the first supporting elements are mechanically connected to the third supporting elements, wherein the second contacts are electrically connected to the fifth contacts, and wherein the second supporting elements are mechanically connected to the fourth supporting elements, so that the first electronic component, the second electronic component, and the connecting structure are connected electrically and mechanically; removing a part of the interposer substrate so that the third contacts are exposed.

A surface treatment solution includes a fluoride source; a first solvent; and a water transforming agent to transform water produced during wafer surface treatment into a second solvent, which can be the same as, or different from, the first solvent. The solution can be used, for example, in surface preparation for wafers having a backend including an electrical interconnect that includes aluminum or an aluminum alloy.

A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

Disclosed are multi-junction light emitting diode (LED) formed by using eutectic bonding and method of manufacturing the multi-junction LED. The multi-junction LED is formed by stacking a separately formed light emitting structure on another light emitting structure by using eutectic bonding. Since separately grown light emitting structure is stacked on the light emitting structure using the eutectic metal alloy bonding, it is possible to prevent crystal defects occurring between the light emitting structures when sequentially grown. Further, since the eutectic metal alloy can be formed in various patterns, it is possible to control and optimize adhesive strength, transmittance of the light generated in the upper light emitting structure, and resistance.

Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.

Wafer-level (chip-scale) package semiconductor devices are described that have bump assemblies configured to maintain standoff (bump) height. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having an array of bump assemblies disposed over the integrated circuit chip. The array of bump assemblies comprises a plurality of first bump assemblies that include solder bumps composed at least substantially of a solder composition (i.e., do not include a core). The array further includes at least one second bump assembly including a solder bump having a core configured to maintain standoff height of the wafer-level package device.

A semiconductor package including: a lower chip; a chip structure including stacked semiconductor chips; and an adhesive film, the semiconductor chips include first bonding chips bonded to each other by bumps and second bonding chips directly bonded to each other, the first bonding chips include: a first bonding lower chip including a first bonding upper pad; and a first bonding upper chip on the first bonding lower chip and including a first bonding lower pad, the second bonding chips include: a second bonding lower chip including a second bonding upper insulating layer and a second bonding upper pad; and a second bonding upper chip on the second bonding lower chip and including a second bonding lower insulating layer, and a second bonding lower pad, and the adhesive film surrounds side surfaces of the bumps, fills a region between the first bonding lower and upper chips, and protrudes from the region.

An aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes preparing a lead frame. The lead frame includes a first lead including a pad and a first terminal. The pad includes a pad main surface and a pad back surface that face opposite sides to each other in a first direction. The first terminal extends from the pad along a second direction that is perpendicular to the first direction. The method includes: preparing a first semiconductor element and a second semiconductor element, each of the first semiconductor element and the second semiconductor element having an element main surface and an element back surface that face opposite sides to each other; die bonding the element back surface of the first semiconductor element to the pad main surface by using a first solder; and die bonding the element back surface of the second semiconductor element to the pad main surface by using a second solder having a melting point lower than a melting point of the first solder, after die bonding the element back surface of the first semiconductor element to the pad main surface by using the first solder.

An optoelectronic device (50) comprising a semiconductor body (10a, 10b, 10c) having an optically active region (12), a carrier (60), and a pair of connection layers (30a, 30b, 30c) having a first connection layer (32) and a second connection layer (34), wherein: the semiconductor body is disposed on the carrier, the first connection layer is disposed between the semiconductor body and the carrier and is connected to the semiconductor body, the second connection layer is disposed between the first connection layer and the carrier, at least one layer selected from the first connection layer and the second connection layer contains a radiation-permeable and electrically conductive oxide, and the first connection layer and the second connection layer are directly connected to each other at least in regions in one or more bonding regions, so that the pair of connection layers is involved in the mechanical connection of the semiconductor body to the carrier. A production process is also specified.