Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure, which includes a plurality of first NAND memory strings, a plurality of first BLs, at least one of the first BLs being conductively connected to a respective one of the first NAND memory strings; and a first bonding layer having a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs, respectively. The 3D memory device further includes a second semiconductor structure, which includes a plurality of second NAND memory strings, a plurality of second BLs, at least one of the second BLs being conductively connected to a respective one of the second NAND memory strings, and a second bonding layer having a plurality of second bit line bonding contacts conductively connected to the plurality of second BLs, respectively.

A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.

A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.

A method of manufacturing a semiconductor structure is provided. The method includes providing a substrate, disposing a die over the substrate, forming a molding over the substrate and around the die, disposing a first dielectric layer over the die and the molding, curing the first dielectric layer under a first curing condition, disposing a second dielectric layer over the first dielectric layer, and curing the first dielectric layer and the second dielectric layer under the first curing condition.

In some embodiments, a semiconductor package includes a package substrate, a plurality of semiconductor chips on the package substrate, a plurality of interposers between the package substrate and the plurality of semiconductor chips, and a molding layer in contact with the plurality of semiconductor chips and the plurality of interposers. The plurality of semiconductor chips includes a first semiconductor chip, and a second and a third semiconductor chip spaced apart from the first semiconductor chip in horizontal directions. The plurality of interposers includes a first vertical connection interposer vertically overlapping the first semiconductor chip, a second vertical connection interposer vertically overlapping the second semiconductor chip, a first horizontal connection interposer vertically overlapping the first and the second semiconductor chips, and a second horizontal connection interposer vertically overlapping the second and the third semiconductor chips.

In an embodiment, a method includes: attaching a package component to a package substrate, the package component includes: a first die being disposed over an interposer; a second die being disposed over the interposer and laterally adjacent to the first die; and an encapsulant being disposed around the first die and the second die; attaching a thermal interface material to the first die and the second die; and attaching a lid structure to the package substrate, the lid structure includes: a lid cap being disposed over the thermal interface material; and a plurality of lid feet connecting the lid cap to the package substrate, in a plan view the plurality of lid feet forming a discontinuous loop around the package component.

A semiconductor device may include: a first semiconductor structure including a first conductive layer and four first bonding pads connected to the first conductive layer; and a second semiconductor structure including a second conductive layer and four second bonding pads connected to the second conductive layer, wherein the four first bonding pads are configured to be disposed to have respective centers each overlapping four intersections that are formed by two virtual first straight lines extending in parallel in a first direction and two virtual second straight lines extending in parallel in a second direction intersecting the first direction, where each of the four first bonding pads has four quadrants divided by the first straight line and the second straight line, and wherein, when the first semiconductor structure and the second semiconductor structure are normally aligned, the four second bonding pads are configured to be disposed to have respective centers that are displaced in directions from the respective centers of the four first bonding pads toward different quadrants.

A semiconductor device includes a first substrate, a logical circuit, a first insulating film, a wiring, a plug, and a first layer containing a metal oxide or a metal nitride. The logical circuit is disposed on the first substrate. The first insulating film is disposed above the logical circuit. The wiring includes a first film disposed in the first insulating film, the first film extending in a first direction along an upper surface of the first substrate, and the first film containing a metal, and a first metal layer disposed in the first insulating film via the first film. The plug is disposed under the wiring, extends in a second direction that intersects the first direction, and is electrically connected to the wiring. The first layer is provided between an upper end of the plug and a bottom end of the wiring.

A semiconductor package may include a lower structure, a first semiconductor chip on the lower structure, the first semiconductor chip including a hot spot, a second semiconductor chip horizontally spaced apart from the first semiconductor chip on the lower structure, and a connection chip in the lower structure and connecting the first and second semiconductor chips to each other. The hot spot may vertically overlap the connection chip.

A semiconductor package may include a package substrate having a first surface and a second surface vertically opposite to each other, a first mounting region and a second mounting region horizontally spaced apart from each other, and first and second semiconductor devices respectively mounted on the first and second mounting regions on the first surface of the package substrate. The package substrate may include wiring patterns electrically connected to the first and second semiconductor devices, dummy patterns electrically insulated from the first and second semiconductor devices, and a reinforcing structure that extends along perimeters of the first and second mounting regions on the first surface of the package substrate, and is bonded to at least portions of the dummy patterns.