Disclosed examples include integrated circuits with a leadframe structure, a first circuit structure including a light source configured to generate a light signal along an optical path, a second circuit structure including a light sensor facing the optical path to receive the light signal, and a molded package structure enclosing portions of the leadframe structure, the molded package structure having a cavity defined by an interior surface of the molded package structure, the optical path extending in the cavity between the first and second circuit structures.

An antenna device and a method of manufacturing the antenna device are provided. The antenna device includes a circuit board, a chip, an encapsulation layer, and an antenna. The circuit board includes an insulation substrate having an upper surface, a lower surface, and a groove formed on the upper surface; a conductive circuit disposed in the insulation substrate; a first conductive pad disposed in the insulation substrate, connected to the conductive circuit, and exposed from the lower surface; a second conductive pad connected to the conductive circuit, and exposed from the groove; and a third conductive pad exposed from the groove. The chip is disposed in the groove, connected to the second conductive pad, and coupled to the third conductive pad. The encapsulation layer is disposed in the groove, and covers the chip.

A wiring substrate includes a buried substrate disposed within a through-hole penetrating through a resin substrate of a core layer and including a plate-like body and a plurality of linear conductors penetrating the plate-like body, a first insulating layer covering a first surface of the resin substrate, a first wiring layer including a first pad pattern formed on a first surface of the buried substrate and a first wiring pattern formed on a first surface of the first insulating layer, and a third wiring pattern formed on the first surface of the resin substrate and covered by the first insulating layer. In the plurality of linear conductors, a gap between the adjacent linear conductors is smaller than a diameter of each of the linear conductors. The third wiring pattern is formed so as to have a thickness thicker than a thickness of the first wiring pattern.

A side-exposed embedded trace substrate includes a dielectric layer, a first wiring layer and a first wiring layer embedded in the dielectric layer. An outer surface of the first wiring layer is not higher than a surface of the dielectric layer, and the first wiring layer includes a pad having a groove to increase a side-exposed area of the pad. The contact area between the substrate and the solder during package welding is increased so that the welding reliability is enhanced, the problem of poor welding or poor reliability caused by trace embedding may be avoided, and poor filling of the packaging material due to insufficient gap between the device and the pad during packaging may be prevented.

A semiconductor package includes: a substrate including a chip region and an edge region extending around the chip region; a plurality of film wirings on the substrate in the chip region; an input wiring and an output wiring on the substrate in the edge region and extending to the chip region in a direction parallel to an upper surface of the substrate; and a semiconductor chip on the substrate in the chip region and electrically connected to the input wiring and the output wiring. The substrate includes a through hole extending through the substrate in a second direction perpendicular to the first direction, and the through hole is between the film wirings.

Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small.

A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

An integrated circuit substrate for surface mounting an integrated circuit component thereon, wherein the integrated circuit substrate comprises a central section, and at least two vertically stacked functional volume sections in the central section, wherein a pitch at an integrated circuit component mounting side of the integrated circuit substrate is not more than 150 m.

A device includes a core including an upper core dielectric layer, a lower core dielectric layer, a central core dielectric layer contacting the upper core dielectric layer and the lower core dielectric layer, and a passive electronic component embedded within the central core dielectric layer. The device includes an upper laminate stack coupled to the upper core dielectric layer. The upper laminate stack includes upper metal layers and contact pads configured to electrically connect a die to the passive electronic component by way of conductive paths defined by the set of upper metal layers. The device includes a lower laminate stack coupled to a bottom surface of the lower core dielectric layer. The lower laminate stack includes lower metal layers and a set of lower dielectric layers disposed between adjacent metal layers of the set of lower metal layers.