The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate, a first bonding layer on the surface of first substrate, the material of first bonding layer includes dielectrics such as Si, N and C, and the first bonding layer of semiconductor structure is provided with higher bonding force in wafer bonding.

The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate, a first adhesive/bonding stack on the surface of first substrate, wherein the first adhesive/bonding stack includes at least one first adhesive layer and at least one first bonding layer. The material of first bonding layer includes dielectrics such as silicon, nitrogen and carbon, the material of first adhesive layer includes dielectrics such as silicon and nitrogen, and the first adhesive/bonding stack of semiconductor structure is provided with higher bonding force in bonding process.

Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.

A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization.

A method for making a photolithography mask for formation of electrically conducting contact pads between tracks of a metallization level and electrically active zones of integrated circuits formed on a semiconductor wafer includes forming a first mask region including first opening zones intended for the formation of the contact pads. The first opening zone has a first degree of opening that is below a threshold. A second mask region including additional opening zones is formed, with the overall degree of opening of the mask being greater than or equal to the threshold.

The present disclosure provides a manufacturing method of a die-stack structure including follow steps. A first wafer including a first die is provided, wherein the first die includes a first substrate material layer, a first interconnect structure, and a first pad, and the first interconnect structure and the first pad are formed on the first substrate material layer in order, and the first substrate material layer has a first contact conductor disposed therein. The first contact conductor is disposed in the first substrate material layer. A second wafer including a second die is provided, wherein the second die includes a second substrate material layer, a second interconnect structure, and a second pad, and the second interconnect structure and the second pad are formed on the second substrate material layer in order, and the second substrate material layer has a second contact conductor disposed therein. A portion of the first substrate material layer is removed to form a first substrate, wherein the first contact conductor is exposed to a surface of the first substrate away from the first interconnect structure. The second wafer is covered on the first substrate such that the first contact conductor is directly physically in contact with the second pad.

A metal-dielectric bonding method includes providing a first semiconductor structure including a first semiconductor layer, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, where the first metal layer has a metal bonding surface facing away from the first semiconductor layer; planarizing the metal bonding surface; applying a plasma treatment on the metal bonding surface; providing a second semiconductor structure including a second semiconductor layer, and a second dielectric layer on the second semiconductor layer, where the second dielectric layer has a dielectric bonding surface facing away from the second semiconductor layer; planarizing the dielectric bonding surface; applying a plasma treatment on the dielectric bonding surface; and bonding the first semiconductor structure with the second semiconductor structure by bonding the metal bonding surface with the dielectric bonding surface.

A chip-stack structure including a first chip and a second chip located on the first chip is provided. The first chip includes a first substrate, a first interconnect structure, a first pad, and a first contact conductor. The first interconnect structure is located on a first surface of the first substrate. The first pad is located on the first interconnect structure. The first contact conductor is located in the first substrate and exposed on a second surface of the first substrate opposite to the first surface. The second chip includes a second substrate, a second interconnect structure, a second pad, and a second contact conductor. The second interconnect structure is located on the second substrate. The second pad is located on the second interconnect structure. The second contact conductor is located in the second substrate, wherein the first contact conductor is directly physically in contact with the second pad.

Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. At least one of a first test pad of the first die or a second test pad of the second die has a protrusion of the at least one of the first test pad or the second test pad, and a bonding insulating layer of the hybrid bonding structure covers and contacts with the protrusion, so that the first test pad and the second test pad are electrically isolated from each other.

A chip-stack structure including a first chip and a second chip located on the first chip is provided. The first chip includes a first substrate, a first interconnect structure, a first pad, and a first contact conductor. The first interconnect structure is located on a first surface of the first substrate. The first pad is located on the first interconnect structure. The first contact conductor is located in the first substrate and exposed on a second surface of the first substrate opposite to the first surface. The second chip includes a second substrate, a second interconnect structure, a second pad, and a second contact conductor. The second interconnect structure is located on the second substrate. The second pad is located on the second interconnect structure. The second contact conductor is located in the second substrate, wherein the first contact conductor is directly physically in contact with the second pad.