A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other.

Dies and/or wafers including conductive features at the bonding surfaces are stacked and direct hybrid bonded at a reduced temperature. The surface mobility and diffusion rates of the materials of the conductive features are manipulated by adjusting one or more of the metallographic texture or orientation at the surface of the conductive features and the concentration of impurities within the materials.

A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a plurality of second transistors, where the second level includes a third layer, the third layer including first conductive lines; a third level overlaying the second level, where the third level includes a plurality of third transistors, where the third level includes a fourth layer, the fourth layer including second conductive lines; and a plurality of connection paths, where the plurality of connection paths provides electrical connections at least from a plurality of the first transistors to the plurality of third transistors, and where the first level includes at least one voltage regulator.

Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes a metal barrier layer plated onto a functional copper layer etched to form the conductive circuit. The conductive circuit has a thickness of less than or equal to 3 m. Further disclosed is a method of making a semiconductor device.

Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal, and the other component has silicon (410) which reacts with the metal to form metal silicide (504). Then a hole (510) is made through one of the components to reach the metal silicide and possibly even the unreacted metal (110C) of the other component. The hole is filled with a conductor (130), possibly metal, to provide a conductive via that can be electrically coupled to contact pads (120C.B) attachable to other circuit elements or microelectronic components, e.g. to a printed circuit board.

Disclosed herein is a method for forming a semiconductor package. The method includes providing a first releasable chip carrier attached to a conductive layer. A circuit layer is formed on a surface of the conductive layer and a dielectric layer is applied over a surface of the circuit layer. A second releasable chip carrier is attached to a surface of the dielectric layer and the first releasable chip carrier is released from the conductive layer via facilitation of a first activating source. The circuitry of the circuit layer is operationally tested.

The present invention relates to a display apparatus using, for example, a micro light emitting diode (LED), and a manufacturing method therefor, wherein the apparatus and method can be applied to a technical field related to display apparatuses. In order to achieve the above objective, a display apparatus according to an embodiment of the present invention comprises: a substrate on which a plurality of unit pixel areas are defined; a wiring electrode positioned on the substrate and positioned in each of the unit pixel areas; a light emitting device that has a device electrode electrically connected to the wiring electrode and is assembled in each of the unit pixel areas; and a coupling forming portion providing a coupling force by which the light emitting device is coupled to the unit pixel areas, wherein the coupling forming portion comprises: an active portion coupled to the light emitting device; and a coupling portion which forms a chemical bond with the active portion and is patterned on the substrate.

Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes an interconnect joint structure in the substrate creating a capture pad including a middle copper layer, an adjacent top nickel layer, and an adjacent bottom nickel layer. A method for making a semiconductor device is further disclosed.

There is provided a semiconductor device, including a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a bonding electrode formed on a surface of the interlayer insulating layer, and a metal film which covers an entire surface of a bonding surface including the interlayer insulating layer and the bonding electrode.