An alignment carrier, assembly and methods that enable the precise alignment and assembly of two or more semiconductor die using an interconnect bridge. The alignment carrier includes a substrate composed of a material that has a coefficient of thermal expansion that substantially matches that of an interconnect bridge. The alignment carrier further includes a plurality of solder balls located on the substrate and configured for alignment of two or more semiconductor die.

A memory device includes a first wafer including a first bonding pad disposed on a first surface; a second wafer, including a second bonding pad disposed on a second surface of the second wafer, the second surface of the second wafer bonded on the first surface of the first wafer; and a first test pattern. The first test pattern includes a pair of first test pads disposed on the first surface and electrically coupled to each other; a pair of second test pads disposed on the second surface of the second wafer and respectively coupled to the pair of first test pads, when no misalignment failure between the first bonding pad and the second bonding pad occurs; and a pair of third test pads disposed on a third surface of the second wafer, which is opposite to the second surface, and respectively coupled to the pair of second test pads.

According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.

The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.

Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

A semiconductor package is provided. The semiconductor package includes a first conductive layer, a plurality of first conductive pads, a plurality of second conductive pads, and a first dielectric layer. The first conductive pads are electrically connected to the first conductive layer. The second conductive pads are electrically disconnected from the first conductive layer.

A semiconductor storage device includes a first chip bonded to a second chip. The first chip includes electrode layers stacked in a first direction, a pillar extending through the stacked electrode layers and including a semiconductor film, and a memory film between the semiconductor film and the electrode layers. The second chip includes a semiconductor substrate having transistors formed thereon, a wiring connected to the transistors and between the semiconductor substrate and the first chip, bonding pads at a level closer to the first chip than the transistors. The bonding pads have a bonding surface facing away from the first chip. An opening extends through the semiconductor substrate to the bonding surface of the bonding pad.

A memory device includes a first wafer including a first bonding pad disposed on a first surface; a second wafer, including a second bonding pad disposed on a second surface of the second wafer, the second surface of the second wafer bonded on the first surface of the first wafer; and a first test pattern. The first test pattern includes a pair of first test pads disposed on the first surface and electrically coupled to each other; a pair of second test pads disposed on the second surface of the second wafer and respectively coupled to the pair of first test pads, when no misalignment failure between the first bonding pad and the second bonding pad occurs; and a pair of third test pads disposed on a third surface of the second wafer, which is opposite to the second surface, and respectively coupled to the pair of second test pads.

A semiconductor memory device includes a first chip having a first pad and a first misalignment detection pattern on a first surface; and a second chip having a second pad and a second misalignment detection pattern on a second surface, and bonded to the first surface of the first chip such that the second pad is coupled with the first pad. The second chip includes a misalignment detection circuit which is coupled between the second misalignment detection pattern and a test pad and outputs a first voltage provided from the first misalignment detection pattern, to the test pad, in the case where a misalignment between the first chip and the second chip exceeds a preset value such that the first misalignment detection pattern and the second misalignment detection pattern are shorted to each other.