A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

A semiconductor package including: a base layer; a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including a plurality of semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack and chip identification pads for identifying the plurality of semiconductor chips in each of the first and second chip stacks; a first inter-chip wire and a second inter-chip wire connecting power-applied ones of the chip identification pads of the plurality of semiconductor chips of the first and second chip stacks; a first stack wire and second stack wire connecting the chip identification pad of a lowermost semiconductor chip of the first and second chip stacks to the base layer.

A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.

A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.

A semiconductor package including: a base layer; a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including a plurality of semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack and chip identification pads for identifying the plurality of semiconductor chips in each of the first and second chip stacks; a first inter-chip wire and a second inter-chip wire connecting power-applied ones of the chip identification pads of the plurality of semiconductor chips of the first and second chip stacks; a first stack wire and second stack wire connecting the chip identification pad of a lowermost semiconductor chip of the first and second chip stacks to the base layer.

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

A semiconductor storage device includes first and second chips. The first chip has first bonding electrodes on a first surface. The second chip has second bonding electrodes on a second surface. The first surface is bonded to the second surface and the first bonding electrodes are electrically connected to the second bonding electrodes. One of the first and second chips has a first bonding pad electrode connectable to a bonding wire for data input/output. A first one of the first bonding electrodes is electrically connected to the first bonding pad electrode. The first chip has, on the first surface, a first insulating layer surrounding the first one of the first bonding electrodes and a second insulating layer that is farther from the first one of the first bonding electrodes than the first insulating layer and formed of a material different from that of the first insulating layer.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first IC chip bonded to a second IC chip. The first chip IC includes a first bond structure. The first bond structure includes a first plurality of conductive bond pads and a first plurality of shield structures disposed between adjacent conductive bond pads among the first plurality of conductive bond pads. The second IC chip includes a second bond structure. A bonding interface is disposed between the first bond structure and the second bond structure. The second bond structure includes a second plurality of conductive bond pads and a second plurality of shield structures. The first plurality of conductive bond pads contacts the second plurality of conductive bond pads and the first plurality of shield structures contacts the second plurality of shield structures at the bonding interface.