A reinforcing resin composition includes an epoxy resin (A), a phenolic resin (B), and a benzoxazine compound (C).

A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

A method of hybridizing an FPA having an IR component and a ROIC component and interconnects between the two components, includes the steps of: providing an IR detector array and a Si ROIC; depositing a dielectric layer on both the IR detector array and on the Si ROIC; patterning the dielectric on both components to create openings to expose contact areas on each of the IR detector array and the Si ROIC; depositing indium to fill the openings on both the IR detector array and the Si ROIC to create indium bumps, the indium bumps electrically connected to the contact areas of the IR detector array and the Si ROIC respectively, exposed on a top surface of the IR detector array and the Si ROIC; activating exposed dielectric layers on the IR detector array and the Si ROIC in a plasma; and closely contacting the indium bumps of the IR detector array and the Si ROIC by bonding together the exposed dielectric surfaces of the IR detector array and the Si ROIC. Another exemplary method provides a pillar support of the indium bumps on the IR detector array rather than a full dielectric layer support. Another exemplary method includes a surrounding dielectric edge support between the IR detector array and the Si ROIC with the pillar supports.

A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad.

The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

A semiconductor package includes a first chip, an insulating protection layer, a second chip, a plurality of second conductive bumps and an underfill. The insulating protection layer is disposed on a first active surface of the first chip and includes a concave. Projections of a plurality of first inner pads and a plurality of first outer pads of the first chip projected on the insulating protection layer are located in the concave and out of the concave, respectively. The second chip is flipped on the concave and includes a plurality of second pads. Each of the first inner pads is electrically connected to the corresponding second pad through the corresponding second conductive bump. The underfill is disposed between the concave and the second chip and covers the second conductive bumps.

Disclosed is a fan-out back-to-back chip stacked package, comprising a back-to-back stack of a first chip and a second chip, an encapsulant, a plurality of vias disposed in the encapsulant, a first redistribution layer and a second redistribution layer. The encapsulant encapsulates the sides of the first chip and the sides of the second chip simultaneously and has a thickness not greater than the chip stacked height to expose a first active surface of the first chip and a second active surface of the second chip. The encapsulant has a first peripheral surface expanding from the first active surface and a second peripheral surface expanding from the second active surface. The first redistribution layer is formed on the first active surface and extended onto the first peripheral surface to electrically connect the first chip to the vias in the encapsulant. The second RDL is formed on the second active surface and extended onto the second peripheral surface to electrically connect the second chip to the vias in the encapsulant. Accordingly, the structure realizes a thin package configuration of multi-chip back-to-back stacking to reduce package warpage.

A semiconductor device includes a substrate, a pad disposed on the substrate, a passivation disposed over the substrate, a post passivation interconnection (PPI) disposed over the passivation and the substrate, a conductive line isolated from the PPI, a bump disposed on the PPI and a polymeric composite between the PPI and the conductive line, wherein the polymeric composite includes a first layer conformal to the conductive line and PPI and a second layer filling a gap between the PPI and the conductive line. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a passivation over the substrate, forming a post passivation interconnect (PPI) and a conductive line over the passivation, disposing a bump on the PPI, and forming a polymeric composite over the PPI by disposing a first layer conformal to the PPI and the conductive line and disposing a second layer to fill a gap between the PPI and the conductive line.

Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar such that during solder reflow, solder wetting of sidewall of the pillar is minimized or prevented all together. The die interconnect may also include a low wetting layer formed on the wetting barrier, which can further mitigate solder wetting problems.