A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.

In an embodiment, a method comprises: configuring a direct conversion compound semiconductor sensor over a first surface of a readout integrated circuit, IC, comprising two surfaces, each surface comprising solder material on the surface; illuminating the solder material with an infra-red laser such that the solder material on the readout IC melts and forms solder joints between the readout IC and the direct conversion compound semiconductor sensor; configuring a substrate over a second surface of the readout IC comprising solder material; and illuminating the solder material of the second surface with the infra-red laser such that the solder material on the readout IC melts and electrically connects the readout IC with the substrate. In other embodiments, a high frequency radiation detector and an imaging apparatus are discussed.

Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

A method for fabricating a resist structure is presented. The method includes preparing a substrate on which plural conductive pads are formed; and patterning a lower resist to form plural lower cavities. The lower resist is deposited above the substrate. Each of the plural lower cavities are located above a corresponding one of the plural conductive pads. Additionally, the method includes patterning an upper resist to form plural upper cavities. The upper resist is deposited on the lower resist. Each of the plural upper cavities are located on a corresponding one of the plural lower cavities and have a diameter larger than a diameter of the corresponding one of the plural lower cavities.

The present invention includes a method for creating a system in a package with integrated lumped element devices and active devices on a single chip/substrate for heterogeneous integration system-on-chip (HiSoC) in photo-definable glass, comprising: masking a design layout comprising one or more electrical passive and active components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass.

Semiconductor devices having an array of flexible connectors configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor assembly includes a substrate coupled to an array of flexible connectors. Each flexible connector can be transformed between a resting configuration and a loaded configuration. Each flexible connector can include a conductive wire electrically coupled to the substrate and a support material at least partially surrounding the conductive wire. The conductive wire can have a first shape when the flexible connector is in the resting configuration and a second, different shape when the flexible connector is in the loaded configuration.

In conventional fluid discharge devices, a discharge head used should be increased in size according to increase in size of a workpiece such as silicon wafer. However, if the discharge head increases in length, a deformation amount of a mask used for discharging the fluid on the workpiece increases, thereby the discharging amount varies. Discharging the fluid in a reciprocating manner is performed using a fluid discharging device including a head unit having a width shorter than a length of the workpiece. A suction port having opening portions each having a slit shape are disposed on the both sides of the discharge nozzle in a vicinity of the discharge nozzle.

An assembly includes at least one first element comprising at least one first electrical bonding pad; at least one second element comprising at least one second electrical bonding pad; electrical and mechanical interconnect means, wherein the electrical and mechanical interconnect means comprise at least: at least one first intermediate metal interconnect element, on the surface of at least the first electrical bonding pad; at least one sintered joint of metal microparticles or nanoparticles stacked with the first intermediate metal interconnect element; the melting point of the first intermediate metal interconnect element being greater than the sintering temperature of the metal microparticles or nanoparticles. A method for fabricating an assembly is also provided.

Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.