Embodiments of the disclosure provide an interconnect structure including: a first die having a first surface and an opposing second surface, and a groove within first surface of the first die; an adhesive dielectric layer mounted to the opposing second surface of the first die; a second die having a first surface mounted to the adhesive dielectric layer, and an opposing second surface, wherein the adhesive dielectric layer is positioned directly between the first and second dies; and a through-semiconductor via (TSV) including a first TSV metal extending from the first surface of the first die to the adhesive dielectric layer, and a second TSV metal substantially aligned with the first TSV metal and extending from the adhesive dielectric layer to the opposing second surface of the second die, wherein the TSV includes a metal-to-metal bonding interface between the first and second TSV metals within the adhesive dielectric layer.

Embodiments of the disclosure provide an interconnect structure including: a first die having a first surface and an opposing second surface, and a groove within first surface of the first die; an adhesive dielectric layer mounted to the opposing second surface of the first die; a second die having a first surface mounted to the adhesive dielectric layer, and an opposing second surface, wherein the adhesive dielectric layer is positioned directly between the first and second dies; and a through-semiconductor via (TSV) including a first TSV metal extending from the first surface of the first die to the adhesive dielectric layer, and a second TSV metal substantially aligned with the first TSV metal and extending from the adhesive dielectric layer to the opposing second surface of the second die, wherein the TSV includes a metal-to-metal bonding interface between the first and second TSV metals within the adhesive dielectric layer.

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.

A printed structure comprises a device comprising device electrical contacts disposed on a common side of the device and a substrate non-native to the device comprising substrate electrical contacts disposed on a surface of the substrate. At least one of the substrate electrical contacts has a rounded shape. The device electrical contacts are in physical and electrical contact with corresponding substrate electrical contacts. The substrate electrical contacts can comprise a polymer core coated with a patterned contact electrical conductor on a surface of the polymer core. A method of making polymer cores comprising patterning a polymer on the substrate and reflowing the patterned polymer to form one or more rounded shapes of the polymer and coating and then patterning the one or more rounded shapes with a conductive material.