A package structure is provided. The package structure includes a first package component and a second package component. The second package component includes a substrate and an electronic component disposed on the substrate, and the first package component is mounted to the substrate. The package structure further includes a ring structure disposed on the second package component and around the first package component. The ring structure has a first foot and a second foot, the first foot and the second foot extend toward the substrate, the electronic component is covered by the ring structure and located between the first foot and the second foot, and the first package component is exposed from the ring structure.

The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion.

The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion.

The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad. The semiconductor device also includes a dielectric liner disposed between the first spacer and the bonding pad; and a first passivation layer covering the second spacer, wherein the dielectric liner is L-shaped, and the first spacer is separated from the bonding pad by the dielectric liner.

The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad. The semiconductor device also includes a dielectric liner disposed between the first spacer and the bonding pad; and a first passivation layer covering the second spacer, wherein the dielectric liner is L-shaped, and the first spacer is separated from the bonding pad by the dielectric liner.

Contact bumps between a contact pad and a substrate can include a rough surface that can mate with the material of the substrate of which may be flexible. The rough surface can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart label and may be formed via roller or other methods.

Contact bumps between a contact pad and a substrate can include a rough surface that can mate with the material of the substrate of which may be flexible. The rough surface can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart label and may be formed via roller or other methods.

A representative system and method for manufacturing stacked semiconductor devices includes disposing an aqueous alkaline solution between a first semiconductor device and a second semiconductor device prior to bonding. In a representative implementation, first and second semiconductor devices may be hybrid bonded to one another, where dielectric features of the first semiconductor device are bonded to dielectric features of the second semiconductor device, and metal features of the first semiconductor device are bonded to metal features of the second semiconductor device. Immersion bonds so formed demonstrate a substantially lower incidence of delamination associated with bond defects.

A semiconductor package includes first and second package components stacked upon and electrically connected to each other, and first and second joint structures. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps having dimensions greater than those of the first and second conductive bumps. The first joint structure partially covers the first and third conductive bumps. The second joint structure partially covers the second and the fourth conductive bumps. A first angle between a sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the first conductive bump is greater than a second angle between a sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the second conductive bump.

A semiconductor package includes first and second package components stacked upon and electrically connected to each other, and first and second joint structures. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps having dimensions greater than those of the first and second conductive bumps. The first joint structure partially covers the first and third conductive bumps. The second joint structure partially covers the second and the fourth conductive bumps. A first angle between a sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the first conductive bump is greater than a second angle between a sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the second conductive bump.