Undesired deposition of metals on a lipseal (lipseal plate-out) during electrodeposition of metals on semiconductor substrates is minimized or eliminated by minimizing or eliminating ionic current directed at a lipseal. For example, electrodeposition can be conducted such as to avoid contact of a lipseal with a cathodically biased conductive material on the semiconductor substrate during the course of electroplating. This can be accomplished by shielding a small selected zone proximate the lipseal to suppress electrode-position of metal proximate the lipseal, and to avoid contact of metal with a lipseal. In some embodiments shielding is accomplished by sequentially using lipseals of different inner diameters during electroplating of metals into through-resist features, where a lipseal having a smaller diameter is used during a first electroplating step and serves as a shield blocking electrodeposition in a selected zone. In a second electroplating step, a lipseal of a larger inner diameter is used.

A terminal structure includes a first wiring layer, an insulation layer covering the first wiring layer, an opening extending through the insulation layer and partially exposing the first wiring layer, a via wiring formed in the opening, a second wiring layer connected to the via wiring on the insulation layer, a protective metal layer on the second wiring layer, a solder layer covering the protective metal layer, and an intermetallic compound layer formed at an interface of the protective metal layer and the solder layer. The protective metal layer includes a projection projecting further outward from a side surface of the second wiring layer. The solder layer covers upper and side surfaces of the protective metal layer through the intermetallic compound layer and exposes a side surface of the second wiring layer. The intermetallic compound layer covers the upper and side surfaces of the protective metal layer.

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.

A wiring board includes: an insulating layer; and a connection terminal formed on the insulating layer. The connection terminal includes a first metal layer laminated on the insulating layer, a second metal layer laminated on the first metal layer, a metal pad laminated on the second metal layer, and a surface treatment layer that covers an upper surface and a side surface of the pad and that is in contact with the upper surface of the insulating layer. An end portion of the second metal layer is in contact with the surface treatment layer, and an end portion of the first metal layer is positioned closer to a center side of the pad than the end portion of the second metal layer is to form a gap between the end portion of the first metal layer and the surface treatment layer.

In an embodiment a method for producing a semiconductor component comprising at least one semiconductor chip mounted on a surface, wherein the semiconductor chip is fixed on the surface by applying a solder compound to an assembling surface of the semiconductor chip, applying a metallic adhesive layer to a side of the solder compound facing away from the assembling surface, preheating the surface to a first temperature T1, bringing the metallic adhesive layer into mechanical contact in a solid state with the preheated surface, the metallic adhesive layer at least partially melting while it is brought into mechanical contact with the preheated surface, and subsequently cooling the surface to room temperature, the semiconductor chip being at least partially metallurgically bonded to the surface, and wherein the semiconductor chip is subsequently soldered to the surface to form a resulting solder connection.

In an embodiment a method for producing a semiconductor component comprising at least one semiconductor chip mounted on a surface, wherein the semiconductor chip is fixed on the surface by applying a solder compound to an assembling surface of the semiconductor chip, applying a metallic adhesive layer to a side of the solder compound facing away from the assembling surface, preheating the surface to a first temperature T1, bringing the metallic adhesive layer into mechanical contact in a solid state with the preheated surface, the metallic adhesive layer at least partially melting while it is brought into mechanical contact with the preheated surface, and subsequently cooling the surface to room temperature, the semiconductor chip being at least partially metallurgically bonded to the surface, and wherein the semiconductor chip is subsequently soldered to the surface to form a resulting solder connection.

Semiconductor dice are arranged on a substrate such as a leadframe. Each semiconductor die is provided with electrically-conductive protrusions (such as electroplated pillars or bumps) protruding from the semiconductor die opposite the substrate. Laser direct structuring material is molded onto the substrate to cover the semiconductor dice arranged thereon, with the molding operation leaving a distal end of the electrically-conductive protrusion to be optically detectable at the surface of the laser direct structuring material. Laser beam processing the laser direct structuring material is then performed with laser beam energy applied at positions of the surface of the laser direct structuring material which are located by using the electrically-conductive protrusions optically detectable at the surface of the laser direct structuring material as a spatial reference.

A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.

A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.