A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, and a bump disposed on the conductive pad, wherein the bump has a first top width and a bottom width, the first top width is greater than the bottom width, and a pair of spacers is disposed adjacent to the bump.

A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, and a bump disposed on the conductive pad, wherein the bump has a first top width and a bottom width, the first top width is greater than the bottom width, and a pair of spacers is disposed adjacent to the bump.

A light-emitting diode (LED) array is formed by bonding an LED chip or wafer to a backplane substrate via curved interconnects. The backplane substrate may include circuits for driving the LED's. One or more curved interconnects are formed on the backplane substrate. A curved interconnect may be electrically connected to a corresponding circuit of the backplane substrate, and may include at least a portion with curvature. The LED chip or wafer may include one or more LED devices. Each LED device may have one or more electrical contacts. The LED chip or wafer is positioned above the backplane substrate to spatially align electrical contacts of the LED devices with the curved interconnects on the backplane substrate. The electrical contacts are bonded to the curved interconnects to electrically connect the LED devices to corresponding circuits of the backplane substrate.

A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.

A semiconductor device includes a conductive pattern disposed over a semiconductor substrate, and an interconnect structure disposed over the conductive pattern. The semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. The inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. The semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. The semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern.

A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, and a bump disposed on the conductive pad, wherein the bump has a first top width and a bottom width, the first top width is greater than the bottom width, and a pair of spacers is disposed adjacent to the bump.

A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, and a bump disposed on the conductive pad, wherein the bump has a first top width and a bottom width, the first top width is greater than the bottom width, and a pair of spacers is disposed adjacent to the bump.

A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.