A method to fabricate a land grid array wafer level chip scale package is described. A silicon die is provided. A dielectric layer is deposited on the silicon die. An opening is etched through the dielectric layer to a metal pad on the silicon die. At least one redistribution layer is formed over the dielectric layer and contacting the metal pad. At least one copper post is formed on the at least one redistribution layer and forms a land grid array. The wafer is sawed partially through on scribe lines to form cuts exposing sides of the silicon die. Thereafter, a molding compound is applied over the at least one redistribution layer and in the cuts wherein the molding compound encapsulates top and side surfaces of the silicon die.

Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

A printed structure includes a destination substrate comprising two or more contact pads disposed on or in a surface of the destination substrate, a component disposed on the surface, and two or more electrically conductive connection posts. Each of the connection posts extends from a common side of the component. Each of the connection posts is in electrical and physical contact with one of the contact pads. The component is tilted with respect to the surface of the destination substrate. Each of the connection posts has a flat distal surface.

A printed structure includes a destination substrate comprising two or more contact pads disposed on or in a surface of the destination substrate, a component disposed on the surface, and two or more electrically conductive connection posts. Each of the connection posts extends from a common side of the component. Each of the connection posts is in electrical and physical contact with one of the contact pads. The component is tilted with respect to the surface of the destination substrate. Each of the connection posts has a flat distal surface.

A method for forming a chip package structure is provided. The method includes bonding a first chip structure and a second chip structure to a surface of a substrate. The first chip structure and the second chip structure are spaced apart from each other. There is a first gap between the first chip structure and the second chip structure. The method includes removing a first portion of the first chip structure and a second portion of the second chip structure to form a trench partially in the first chip structure and the second chip structure and partially over the first gap. The method includes forming an anti-warpage bar in the trench. The anti-warpage bar is over the first chip structure, the second chip structure, and the first gap.

An electronic package and a method of manufacture includes a substrate having an upper surface with a trench formed in a bridge region. First pads are arranged on the upper surface of the substrate, outside of the bridge region, and a bridge is positioned in the trench. A plurality of second pads are arranged on an upper surface of the bridge. A plurality of pillars are electrically coupled to the plurality of second pads. Two or more semiconductor chips are positioned in a side-by-side proximal arrangement overlaying the bridge and the substrate. A first semiconductor chip is joined to the bridge, then a second semiconductor chip is joined to the bridge, followed by attaching the chip-bridge assembly to the substrate with the bridge positioned within the substrate trench. Each of the two or more semiconductor chips have first electrical connections including bumps, and second electrical connections including third pads.

A conductive micro pin includes a body having a first end surface, a second end surface, a first side surface connecting the first end surface and the second end surface, and a first corner between the first end surface and the first side surface, in which the first side surface is substantially flat, and the first corner is substantially rounded.

A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

The present invention discloses an ion beam lithography method based on an ion beam lithography system. The ion beam lithography system includes a roll-roll printer placed in a vacuum, and a medium-high-energy wide-range ion source, a medium-low-energy wide-range ion source and a low-energy ion source installed on the roll-roll printer. The ion beam lithography method includes: first coating a polyimide (PI) substrate with a dry film, etching the dry film according to a preset circuit pattern, then using the ion beam lithography system to deposit a wide-energy-range metal ion on the circuit pattern to form a film substrate, and finally stripping the dry film off the film substrate to obtain a printed circuit board (PCB).

An RF circuit module includes a module substrate, a first substrate in which a first circuit is implemented, and a second substrate in which a second circuit is implemented. The first circuit includes a control circuit that controls an operation of the second circuit. The second circuit includes a radio-frequency amplifier circuit that amplifies an RF signal. The second substrate is mounted on the first substrate. The first substrate is disposed on the module substrate such that a circuit forming surface faces the module substrate. The first substrate and the second substrate have a circuit-to-circuit connection wire that electrically connects the first circuit and the second circuit without intervening the module substrate.