A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.

An electronic component mounting method including the steps of: providing a first electronic component having a principal surface provided with a plurality of bumps; providing a substrate having a placement area provided with a plurality of first electrodes corresponding to the plurality of bumps; applying flux to the plurality of bumps; applying flux to at least one of the first electrodes adjacent to at least one reinforcement position set on a peripheral portion of the placement area; dispensing a thermosetting resin onto the reinforcement position, and at least partially coating the first electrode adjacent to the reinforcement position, with the thermosetting resin; placing the first electronic component on the substrate such that the bumps land on the corresponding first electrodes, and thus bringing the thermosetting resin into contact with a peripheral edge portion of the first electronic component; and heating the substrate with the first electronic component placed thereon.

An electronic chip including a support and connection pillars, each connection pillar including a trunk including an end portion and an intermediate portion coupling the end portion to the support, and including a collar at the junction between the end portion and the intermediate portion.

A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.

A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.

A semiconductor package includes a semiconductor die and a redistribution structure. The semiconductor die is laterally surrounded by a molding compound, and the semiconductor die has a conductive pillar and a complex compound sheath sandwiched between the conductive pillar and the molding compound. The redistribution structure is electrically connected with the semiconductor die and comprises a first via portion at a first side of the redistribution structure and a second via portion at a second side of the redistribution structure, and a base angle of the second via portion is greater than a base angle of the first via portion.