A printed structure comprises a device comprising device electrical contacts disposed on a common side of the device and a substrate non-native to the device comprising substrate electrical contacts disposed on a surface of the substrate. At least one of the substrate electrical contacts has a rounded shape. The device electrical contacts are in physical and electrical contact with corresponding substrate electrical contacts. The substrate electrical contacts can comprise a polymer core coated with a patterned contact electrical conductor on a surface of the polymer core. A method of making polymer cores comprising patterning a polymer on the substrate and reflowing the patterned polymer to form one or more rounded shapes of the polymer and coating and then patterning the one or more rounded shapes with a conductive material.

A printed structure comprises a device comprising device electrical contacts disposed on a common side of the device and a substrate non-native to the device comprising substrate electrical contacts disposed on a surface of the substrate. At least one of the substrate electrical contacts has a rounded shape. The device electrical contacts are in physical and electrical contact with corresponding substrate electrical contacts. The substrate electrical contacts can comprise a polymer core coated with a patterned contact electrical conductor on a surface of the polymer core. A method of making polymer cores comprising patterning a polymer on the substrate and reflowing the patterned polymer to form one or more rounded shapes of the polymer and coating and then patterning the one or more rounded shapes with a conductive material.

A printed structure comprises a device comprising device electrical contacts disposed on a common side of the device and a substrate non-native to the device comprising substrate electrical contacts disposed on a surface of the substrate. At least one of the substrate electrical contacts has a rounded shape. The device electrical contacts are in physical and electrical contact with corresponding substrate electrical contacts. The substrate electrical contacts can comprise a polymer core coated with a patterned contact electrical conductor on a surface of the polymer core. A method of making polymer cores comprising patterning a polymer on the substrate and reflowing the patterned polymer to form one or more rounded shapes of the polymer and coating and then patterning the one or more rounded shapes with a conductive material.

The present disclosure relates to the field of semiconductor technology, and discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.

The present disclosure relates to the field of semiconductor technology, and discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.

A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

In a described example, a method for passivating a copper structure includes: passivating a surface of the copper structure with a copper corrosion inhibitor layer; and depositing a protection overcoat layer with a thickness less than 35 μm on a surface of the copper corrosion inhibitor layer.

In a described example, a method for passivating a copper structure includes: passivating a surface of the copper structure with a copper corrosion inhibitor layer; and depositing a protection overcoat layer with a thickness less than 35 μm on a surface of the copper corrosion inhibitor layer.

A first conductive pad is connected to a second conductive pad by using a post-transition metal and a nanoporous metal. An example of the post-transition metal is indium. An example of the nanoporous metal is nanoporous gold. A block of the post-transition metal is formed on the first conductive pad. The block of the post-transition metal is coated with a layer of anti-corrosion material. A block of the nanoporous metal is formed on the second conductive pad. The block of the post-transition metal and the block of the nanoporous metal are thermal compressed to form an alloy between the first conductive pad and the second conductive pad.