A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters.

Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).

A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).

A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters.

A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters.

A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).

A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).

A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.