Provided are a Sn—Bi—In-based low melting-point joining member used in a Pb-free electroconductive joining method in mounting a semiconductor component, and is usable for low-temperature joining, and a manufacturing method therefor.

A Sn—Bi—In-based low melting-point joining member, including a Sn—Bi—In alloy that has a composition within a range represented by a quadrangle in a Sn—Bi—In ternary phase diagram, a first quadrangle having four vertices including: Point 1 (1, 69, 30), Point 2 (26, 52, 22), Point 3 (40, 10, 50), and Point 4 (1, 25, 74), where Point (x, y, z) is defined as a point of x mass % Sn, y mass % Bi and z mass % In, and that also has a melting point of 60 to 110° C. As well as a method for producing a Sn—Bi—In-based low melting-point joining member, including a plating step of forming a plated laminate on an object to be plated, the plated laminate including a laminated plating layer obtained by performing Sn plating, Bi plating, and In plating respectively such that the laminated plating layer has a composition within the range represented by the first quadrangle.

A terminal structure includes a first wiring layer, an insulation layer covering the first wiring layer, an opening extending through the insulation layer and partially exposing the first wiring layer, a via wiring formed in the opening, a second wiring layer connected to the via wiring on the insulation layer, a protective metal layer on the second wiring layer, a solder layer covering the protective metal layer, and an intermetallic compound layer formed at an interface of the protective metal layer and the solder layer. The protective metal layer includes a projection projecting further outward from a side surface of the second wiring layer. The solder layer covers upper and side surfaces of the protective metal layer through the intermetallic compound layer and exposes a side surface of the second wiring layer. The intermetallic compound layer covers the upper and side surfaces of the protective metal layer.

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

An electrical component including a substrate, a first dielectric layer on the substrate, a redistribution layer pad on the first dielectric layer, and a component interconnection element on the redistribution layer pad so that the component interconnection element fills an opening in the second dielectric layer. The opening includes at least one protrusion between the component interconnection element solder ball metallization and the redistribution layer pad.

An electrical component including a substrate, a first dielectric layer on the substrate, a redistribution layer pad on the first dielectric layer, and a component interconnection element on the redistribution layer pad so that the component interconnection element fills an opening in the second dielectric layer. The opening includes at least one protrusion between the component interconnection element solder ball metallization and the redistribution layer pad.

An apparatus and method for manufacturing a semiconductor package structure are provided. The method includes: providing a process line comprising a first semiconductor manufacturing portion configured to provide a first operation including a first process step, and a second semiconductor manufacturing portion configured to provide a second operation including a second process step; passing a packaging structure through the second semiconductor manufacturing portion, wherein the second semiconductor manufacturing portion applies the second process step to the packaging structure; passing the packaging structure through the first semiconductor manufacturing portion, wherein the first semiconductor manufacturing portion applies the first process step to the packaging structure; and passing the packaging structure through the second semiconductor manufacturing portion again without applying the second process step thereon.

Systems and methods for performing reflow modeling in a virtual fabrication environment are discussed. More particularly, the virtual fabrication environment may determine metal or material “reflow” or movement during fabrication of a semiconductor device structure. A reflow modeling step with user-specified parameters may be inserted into a process sequence used during fabrication of the semiconductor device structure.