Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad, a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer, and a second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view. The outer edge portion of the second conductive layer has at least one curved portion. At least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view.

A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface opposite the first surface, a release layer is located above the first surface of the silicon handler wafer, and a layer selected from the group consisting of an adhesive layer and a redistribution layer is located on a surface of the release layer. After building-up a fan-out wafer level package on the support structure, infrared radiation is employed to remove (via laser ablation) the release layer, and thus remove the silicon handler wafer from the fan-out wafer level package.

Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.

A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.

A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.

Provided is an integrated fan-out package including a die, a first redistribution circuit structure, a second redistribution circuit structure, a plurality of solder joints, a plurality of conductive posts, and an insulating encapsulation. The first redistribution circuit structure and the second redistribution circuit structure are formed respectively over a back surface and an active surface of the die to sandwich the die. The solder joints are formed aside the die and connected to the first redistribution circuit structure. The conductive posts are formed on the solder joints and connected to the second redistribution circuit structure, and connected to the first redistribution circuit structure through the solder joints. A plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, and a plurality of sidewalls of the solder joints are encapsulated by the insulating encapsulation. A fabricating process of the integrated fan-out package is also provided.

The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.