Various applications of interconnect substrates in power management systems are described.

Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. A method can include providing a stack in a radio frequency switch arrangement, the stack arranged in relation to a ground plane, the stack including a plurality of switching elements coupled in series with one another, the stack having first and second ends, the first end including a respective terminal of a first one of the plurality of switching elements. The method can also include forming a first solder bump coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement.

Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. A method can include providing a stack in a radio frequency switch arrangement, the stack arranged in relation to a ground plane, the stack including a plurality of switching elements coupled in series with one another, the stack having first and second ends, the first end including a respective terminal of a first one of the plurality of switching elements. The method can also include forming a first solder bump coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement.

A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.

A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.

Transistors including semiconductor regions where operating current flows are provided above a substrate. Operating electrodes of conductive material having thermal conductivity higher than the semiconductor regions and contacting the semiconductor regions to conduct operating current to the semiconductor regions are disposed. A conductor pillar for external connection contains contact regions where the semiconductor regions and the operating electrodes contact, and is electrically connected to the operating electrodes. The contact regions are disposed in a first direction. Each contact region has a planar shape long in a second direction orthogonal to the first direction. A first average distance, obtained by averaging distances in the second direction from each end portion of the contact region in the second direction to an edge of the conductor pillar across the contact regions, exceeds an average distance value in a height direction from the contact region to a top surface of the conductor pillar.

Transistors including semiconductor regions where operating current flows are provided above a substrate. Operating electrodes of conductive material having thermal conductivity higher than the semiconductor regions and contacting the semiconductor regions to conduct operating current to the semiconductor regions are disposed. A conductor pillar for external connection contains contact regions where the semiconductor regions and the operating electrodes contact, and is electrically connected to the operating electrodes. The contact regions are disposed in a first direction. Each contact region has a planar shape long in a second direction orthogonal to the first direction. A first average distance, obtained by averaging distances in the second direction from each end portion of the contact region in the second direction to an edge of the conductor pillar across the contact regions, exceeds an average distance value in a height direction from the contact region to a top surface of the conductor pillar.

An integrated circuit device includes a support substrate, a first semiconductor chip and a second semiconductor chip provided on the support substrate, and a connection member made of solder. The first semiconductor chip and the second semiconductor chip each includes a semiconductor substrate, an interconnect layer provided on the semiconductor substrate, and a pad provided on a side surface of the interconnect layer. The connection member contacts a side surface of the pad of the first semiconductor chip and a side surface of the pad of the second semiconductor chip.

An integrated circuit device includes a support substrate, a first semiconductor chip and a second semiconductor chip provided on the support substrate, and a connection member made of solder. The first semiconductor chip and the second semiconductor chip each includes a semiconductor substrate, an interconnect layer provided on the semiconductor substrate, and a pad provided on a side surface of the interconnect layer. The connection member contacts a side surface of the pad of the first semiconductor chip and a side surface of the pad of the second semiconductor chip.

A semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor (HBT) includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors through respective overlying conductor filled via openings that overlap in a plan view with a width portion of the bump. The semiconductor device reduces heat resistance in an HBT cell by satisfying two conditions, the first of which is related to specific sizing and positioning of a width portion of the overlying via opening relative to the width portion of the bump, and the second of which is related to positioning the base electrode entirely within a specific region of the width portion of the overlapping overlying via opening.