A semiconductor package may be presented. The semiconductor package includes a first dielectric layer including a first surface and a second surface. First and second conductive lands are disposed on the first surface of the first dielectric layer. A first column formed by the first conductive lands and a second column formed by the second conductive lands are spaced apart from each other. Outer traces extend from the second conductive lands, and inner traces are disposed on the second surface of the first dielectric layer. Vias penetrate the first dielectric layer and respectively connect the first conductive lands to the inner traces. A semiconductor die is disposed on the first surface of the first dielectric layer.

A semiconductor package includes a base substrate having a plurality of upper pads and a plurality of first and second lower pads, a semiconductor chip disposed on the base substrate and electrically connected to the plurality of upper pads, a solder resist layer having a plurality of openings exposing a region of each of the plurality of first and second lower pads, the exposed regions of the plurality of first and second lower pads having the same size, a plurality of first external connection conductors respectively disposed on the exposed regions of the plurality of first lower pads and having a first height and a first volume, and a plurality of second external connection conductors respectively disposed on the exposed regions of the plurality of second lower pads and having a second height, greater than the first height, and a second volume, greater than the first volume.

A semiconductor package includes a base substrate having a plurality of upper pads and a plurality of first and second lower pads, a semiconductor chip disposed on the base substrate and electrically connected to the plurality of upper pads, a solder resist layer having a plurality of openings exposing a region of each of the plurality of first and second lower pads, the exposed regions of the plurality of first and second lower pads having the same size, a plurality of first external connection conductors respectively disposed on the exposed regions of the plurality of first lower pads and having a first height and a first volume, and a plurality of second external connection conductors respectively disposed on the exposed regions of the plurality of second lower pads and having a second height, greater than the first height, and a second volume, greater than the first volume.

An interposer includes a base layer having a first surface and a second surface, a redistribution structure on the first surface, an interposer protection layer on the second surface, a pad wiring layer on the interposer protection layer, an interposer through electrode passing through the base layer and the interposer protection layer and electrically connecting the redistribution structure to the pad wiring layer, an interposer connection terminal attached to the pad wiring layer, and a wiring protection layer including a first portion covering a portion of the interposer protection layer adjacent to the pad wiring layer, a second portion covering a portion of a top surface of the pad wiring layer, and a third portion covering a side surface of the pad wiring layer. The third portion is disposed between the first portion and the second portion. The first to third portions have thicknesses different from each other.

An interposer includes a base layer having a first surface and a second surface, a redistribution structure on the first surface, an interposer protection layer on the second surface, a pad wiring layer on the interposer protection layer, an interposer through electrode passing through the base layer and the interposer protection layer and electrically connecting the redistribution structure to the pad wiring layer, an interposer connection terminal attached to the pad wiring layer, and a wiring protection layer including a first portion covering a portion of the interposer protection layer adjacent to the pad wiring layer, a second portion covering a portion of a top surface of the pad wiring layer, and a third portion covering a side surface of the pad wiring layer. The third portion is disposed between the first portion and the second portion. The first to third portions have thicknesses different from each other.

A semiconductor package including: a redistribution layer including redistribution line patterns, redistribution vias connected to the redistribution line patterns, and a redistribution insulating layer surrounding the redistribution line patterns and the redistribution vias; semiconductor chips including at least one upper semiconductor chip disposed on a lowermost semiconductor chip of the semiconductor chips, wherein the at least one upper semiconductor chip is thicker than the lowermost semiconductor chip; bonding wires each having a first end and a second end, wherein the bonding wires connect the semiconductor chips to the redistribution layer, wherein the first end of each of the bonding wires is connected to a respective chip pad of the semiconductor chips and the second end of each of the bonding wires is connected to a respective one of the redistribution line patterns; and a molding member surrounding, on the redistribution layer, the semiconductor chips and the bonding wires.

A semiconductor package including: a redistribution layer including redistribution line patterns, redistribution vias connected to the redistribution line patterns, and a redistribution insulating layer surrounding the redistribution line patterns and the redistribution vias; semiconductor chips including at least one upper semiconductor chip disposed on a lowermost semiconductor chip of the semiconductor chips, wherein the at least one upper semiconductor chip is thicker than the lowermost semiconductor chip; bonding wires each having a first end and a second end, wherein the bonding wires connect the semiconductor chips to the redistribution layer, wherein the first end of each of the bonding wires is connected to a respective chip pad of the semiconductor chips and the second end of each of the bonding wires is connected to a respective one of the redistribution line patterns; and a molding member surrounding, on the redistribution layer, the semiconductor chips and the bonding wires.

Disclosed is a method for manufacturing a flip chip, in which a gold typically used in a flip chip manufacturing is adhered by conductive adhesives, wherein the method comprises steps of depositing a metal seed layer on a substrate; applying and patterning a photoresist or a dry film; forming a gold bump by electroplating; patterning the seed layer; forming an insulating layer on the seed layer and upper end of the gold bump; and patterning an insulating layer. Accordingly, it is possible to manufacture a flip chip, in which electrical function between bumps can be evaluated, with less cost.

The display device includes a flexible base layer including a first region and a second region located around the first; a display unit on one surface of the first region and including a light emitting element; a driving circuit on the second region and including a plurality of first bumps arranged in a first row and a plurality of second bumps arranged in a second row, the driving circuit includes a third bump in the first row and disposed outward relative to the plurality of first bumps, a first and second reference bump each disposed at a center of the plurality of first and second bumps that are disposed along a reference line defined in a column direction vertically intersecting a row direction, the remaining first and second bumps excluding the first reference bump and the second reference bump arranged to have a preset slope with respect to the reference line.

The display device includes a flexible base layer including a first region and a second region located around the first; a display unit on one surface of the first region and including a light emitting element; a driving circuit on the second region and including a plurality of first bumps arranged in a first row and a plurality of second bumps arranged in a second row, the driving circuit includes a third bump in the first row and disposed outward relative to the plurality of first bumps, a first and second reference bump each disposed at a center of the plurality of first and second bumps that are disposed along a reference line defined in a column direction vertically intersecting a row direction, the remaining first and second bumps excluding the first reference bump and the second reference bump arranged to have a preset slope with respect to the reference line.