An electronic device includes a semiconductor die having a first side, an orthogonal second side for mounting to a substrate or circuit board, a conductive terminal on the first side, the conductive terminal having a center that is spaced apart from the second side by a first distance along a direction, and a solder structure extending on the conductive terminal, the solder structure having a center that is spaced apart from the center of the conductive terminal by a non-zero second distance along the direction.

A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

An electronic package includes a pad, a dielectric layer, a bump, and a conductive element. The dielectric layer encapsulates the pad and includes an opening exposing the pad. The bump is disposed over the pad. The conductive element is disposed in the opening between the pad and the bump. The conductive element is configured to mitigate a shrinkage of an electrical path between the pad and the bump occupied by an expansion of the dielectric layer.

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.