A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die. The low stress bumps include multiple polymer layers. More than one type of bump is coupled to a die, with low stress bumps placed on areas subjected to high stress.

Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die. The low stress bumps include multiple polymer layers. More than one type of bump is coupled to a die, with low stress bumps placed on areas subjected to high stress.

Various embodiments provide semiconductor packaging structures and methods for forming the same. In an exemplary method, a chip having a metal interconnect structure thereon can be provided. An insulating layer can be formed on the chip to expose the metal interconnect structure. A columnar electrode can be formed on the metal interconnect structure. A portion of the metal interconnect structure surrounding a bottom of the columnar electrode can be exposed. A diffusion barrier layer can be formed on sidewalls and a top surface of the columnar electrode, and on the exposed portion of the metal interconnect structure surrounding the bottom of the columnar electrode. A solder ball can then be formed on the diffusion barrier layer. The solder ball can wrap at least the sidewalls and the top surface of the columnar electrode.

The present application provides a semiconductor structure having a copper pillar within a solder bump, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate having a pad disposed thereon and a passivation at least partially surrounding the pad; and a conductive bump structure disposed over the passivation and the pad, wherein the conductive bump structure includes a first bump portion disposed over the passivation and the pad, a conductive pillar disposed over the first bump portion, and a second bump portion disposed over and surrounding the conductive pillar.

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

A semiconductor package is provided. The semiconductor package includes: a first stack including a first semiconductor substrate; a through via that penetrates the first semiconductor substrate in a first direction; a second stack that includes a second face facing a first face of the first stack, on the first stack; a first pad that is in contact with the through via, on the first face of the first stack; a second pad including a concave inner side face that defines an insertion recess, the second pad located on the second face of the second stack; and a bump that connects the first pad and the second pad, wherein the bump includes a first upper bump on the first pad, and a first lower bump between the first upper bump and the first pad.

The present application provides a semiconductor structure having a copper pillar within a solder bump, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate having a pad disposed thereon and a passivation at least partially surrounding the pad; and a conductive bump structure disposed over the passivation and the pad, wherein the conductive bump structure includes a first bump portion disposed over the passivation and the pad, a conductive pillar disposed over the first bump portion, and a second bump portion disposed over and surrounding the conductive pillar.

A copper pillar bump (CPB) structure, including a passivation layer covering a substrate and exposing a pad and a copper pillar on the passivation layer and the pad and connecting directly with the pad, wherein a horizontal cross-section of the copper pillar is circle. The copper pillar is provided with an upper part and a lower part, and an upper surface of the lower part includes a first upper surface and a second upper surface. The second upper surface is on one side of the first upper surface, a horizontal cross-section of the second upper surface of the lower part is two diagonally opposite quarter circles, and the upper part of the copper pillar is on the first upper surface of the lower part. A metal bump is on the copper pillar, wherein parts of the metal bump directly contact the second upper surface of the lower part.