A package structure includes a circuit substrate, a semiconductor package, a thermal interface material, a lid structure and a heat dissipation structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The thermal interface material is disposed on the semiconductor package. The lid structure is disposed on the circuit substrate and surrounding the semiconductor package, wherein the lid structure comprises a supporting part that is partially covering and in physical contact with the thermal interface material. The heat dissipation structure is disposed on the lid structure and in physical contact with the supporting part of the lid structure.

Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.

The present disclosure relates to a semiconductor package that may include a substrate. The substrate may have a top surface and a bottom surface. The semiconductor package may include an opening in the substrate. The semiconductor package may include a bridge disposed in the opening. The bridge may have an upper end at the top surface of the substrate and a lower end at the bottom surface of the substrate. The semiconductor package may include a first die on the top surface of the substrate at least partially extending over a first portion of the upper end of the bridge. The semiconductor package may include a second die on the bottom surface of the substrate at least partially extending over the lower end of the bridge. The bridge may couple the first die to the second die.

The present disclosure relates to a solid state micro device structure that has a microdevice formed on a substrate, with p and n doped layers, active layers between at least the two doped layers, pads coupled to each doped layer, and wherein the n-doped layer is modulated to have a lower conductivity towards an edge of the device. The invention further involves, dielectric layer, conductive layer, passivation layer and MIS structure.

A chip for controlled electrostatic discharging to avoid loading on input/output pins, comprising: a die comprising: a first plurality of connector pins each conductively coupled to one or more signal paths, each of the first plurality of connector pins having a first height; and a second plurality of connector pins independent of any signal paths, each of the second plurality of connector pins having a second height greater than the first height.

Undesired deposition of metals on a lipseal (lipseal plate-out) during electrodeposition of metals on semiconductor substrates is minimized or eliminated by minimizing or eliminating ionic current directed at a lipseal. For example, electrodeposition can be conducted such as to avoid contact of a lipseal with a cathodically biased conductive material on the semiconductor substrate during the course of electroplating. This can be accomplished by shielding a small selected zone proximate the lipseal to suppress electrode-position of metal proximate the lipseal, and to avoid contact of metal with a lipseal. In some embodiments shielding is accomplished by sequentially using lipseals of different inner diameters during electroplating of metals into through-resist features, where a lipseal having a smaller diameter is used during a first electroplating step and serves as a shield blocking electrodeposition in a selected zone. In a second electroplating step, a lipseal of a larger inner diameter is used.

A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.

A display device includes an array substrate, a plurality of mounting electrodes provided to the array substrate, a columnar conductor for coupling provided to each of the mounting electrodes, a plurality of light-emitting elements provided to the array substrate, a first electrode and a second electrode provided to a surface of each of the light-emitting elements facing the array substrate, the first electrode being coupled to one of an anode and a cathode of the light-emitting element, the second electrode being coupled to the other of the anode and the cathode of the light-emitting element, and a coupling member covering each of the first electrode and the second electrode. The columnar conductor is made of material harder than the coupling member, and an end of the columnar conductor on the light-emitting element side is electrically coupled to the coupling member.