A semiconductor package includes a first sub-package and a second sub-package. The first sub-package is stacked atop the second sub-package. Each of the first sub-package and the second sub-package includes at least two first semiconductor dies, a second semiconductor die, a plurality of molding pieces, a bond-pad layer, a plurality of redistribution layers (RDLs) and a plurality of bumps. The bumps of the first sub-package are attached to the bond-pad layer of the second sub-package.

A semiconductor package includes a first sub-package and a second sub-package. The first sub-package is stacked atop the second sub-package. Each of the first sub-package and the second sub-package includes at least two first semiconductor dies, a second semiconductor die, a plurality of molding pieces, a bond-pad layer, a plurality of redistribution layers (RDLs) and a plurality of bumps. The bumps of the first sub-package are attached to the bond-pad layer of the second sub-package.

A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.

A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.

A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.

A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.

There is provided a semiconductor device that includes a wiring layer, a plurality of bonding layers arranged on the wiring layer and having conductivity, and a semiconductor element having a rear surface facing the wiring layer and a plurality of pads provided on the rear surface, and bonded to the wiring layer via the plurality of bonding layers, wherein the plurality of bonding layers are arranged in a grid shape when viewed along a thickness direction, wherein each of the plurality of pads is electrically connected to a circuit formed inside the semiconductor element and any of the plurality of bonding layers, and wherein at least one of the plurality of pads is located to be spaced apart from the plurality of bonding layers when viewed along the thickness direction.

There is provided a semiconductor device that includes a wiring layer, a plurality of bonding layers arranged on the wiring layer and having conductivity, and a semiconductor element having a rear surface facing the wiring layer and a plurality of pads provided on the rear surface, and bonded to the wiring layer via the plurality of bonding layers, wherein the plurality of bonding layers are arranged in a grid shape when viewed along a thickness direction, wherein each of the plurality of pads is electrically connected to a circuit formed inside the semiconductor element and any of the plurality of bonding layers, and wherein at least one of the plurality of pads is located to be spaced apart from the plurality of bonding layers when viewed along the thickness direction.

An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.

An integrated circuit (IC) chip comprises a plurality of pads and a plurality of bumps. The plurality of pads includes a first pad. The plurality of bumps is disposed on the plurality of pads. The plurality of bumps includes a first bump disposed on the first pad. The first bump as a width that is different than an exposed with of the first pad. The center of the first bump is not aligned with a center of the first pad.