A photodetector-array and fabrication method thereof are disclosed. The photodetector-array includes a first and second semiconductor structures having respective active regions defining respective pluralities of active photodetectors and active readout integrated circuit pixels (RICPs) electronically connectable to one another respectively. The first and second semiconductor structures are made with different semiconductor materials/compositions having different first and second coefficients of thermal expansion (CTEs) respectively. The pitch distances of the active photodetectors and the pitch distances of the respective active RICPs are configured in accordance with the difference between the first and second CTEs, such that at high temperatures, at which electrical coupling between the first and second semiconductor structures is performed, the electric contacts of the active photodetectors and of their respective RICPs overlap. Accordingly, after the first and second semiconductor structures are bonded together, at least 99.5% of the active photodetector are electrically connected with their respective RICPs.

A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.

A semiconductor device vertically mounted on a medium such as a printed circuit board, and a method of its manufacture, are disclosed. The semiconductor device includes a stack of semiconductor die having contact pads which extend to an active edge of the die aligned on one side of the stack. The active edges of the die are affixed to the PCB and the contact pads at the active edge are electrically coupled to the PCB. This configuration provides an optimal, high density arrangement of semiconductor die in the device, where a large number of semiconductor die can be mounted and electrically coupled directly to the PCT, without a substrate, without staggering the semiconductor die, and without using wire bonds.

A surface-mount component (10A) having a pair of connection terminals (12a, 12b) with an inter-terminal pitch L2 therebetween is mounted on a circuit substrate (20A) having a pair of electrode pads (22a, 22b) with an inter-electrode pitch L1 therebetween (L2>L1). Standard position indication marks (23) are formed on the circuit substrate (20A). When heating is performed under a state in which solder non-wetting of the left electrode pad (22a) occurs, the solder applied to the right electrode pad (22b) solder connects the right electrode pad (22b) and the connection terminal (12b), and the surface-mount component (10A) is attracted to the left and is offset or displaced from the standard position indication marks (23) by an offset dimension 7. If the solder is applied to the left and right electrode pads (22a, 22b), there is no offset dimension.

A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.

A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.

A semiconductor device vertically mounted on a medium such as a printed circuit board, and a method of its manufacture, are disclosed. The semiconductor device includes a stack of semiconductor die having contact pads which extend to an active edge of the die aligned on one side of the stack. The active edges of the die are affixed to the PCB and the contact pads at the active edge are electrically coupled to the PCB. This configuration provides an optimal, high density arrangement of semiconductor die in the device, where a large number of semiconductor die can be mounted and electrically coupled directly to the PCT, without a substrate, without staggering the semiconductor die, and without using wire bonds.

A semiconductor chip includes a semiconductor device with an upper surface and a lower surface opposite to the upper surface. The semiconductor device includes an input terminal, a plurality of through silicon vias, a plurality of selection pads, a plurality of tilt pads and a plurality of tilt conductive structures. The through silicon vias are extended through the semiconductor device. The selection pads are located on the lower surface The tilt pads are located on the upper surface and connected to the selection pads through the through silicon vias respectively. Each tilt pad includes a pad surface that is non-parallel to the upper surface. A lower end of each tilt conductive structure is in contact with the pad surface of each tilt pad, and an upper end of each tilt conductive structure is vertically overlapped with an immediately-adjacent one of the tilt pads.

A surface-mount component (10A) having a pair of connection terminals (12a, 12b) with an inter-terminal pitch L2 therebetween is mounted on a circuit substrate (20A) having a pair of electrode pads (22a, 22b) with an inter-electrode pitch L1 therebetween (L2>L1). Standard position indication marks (23) are formed on the circuit substrate (20A). When heating is performed under a state in which solder non-wetting of the left electrode pad (22a) occurs, the solder applied to the right electrode pad (22b) solder connects the right electrode pad (22b) and the connection terminal (12b), and the surface-mount component (10A) is attracted to the left and is offset or displaced from the standard position indication marks (23) by an offset dimension 7. If the solder is applied to the left and right electrode pads (22a, 22b), there is no offset dimension.

The invention relates to a chip arrangement (18) comprising a terminal substrate (12) and a plurality of semiconductor substrates (1) which are arranged on the terminal substrate, in particular chips, wherein terminal faces (5) arranged on a contact surface of the chips (1) are connected to terminal faces on a contact surface (14) of the terminal substrate (12), wherein the chips (1) extend parallel with a lateral edge and transversally with their contact surface to the contact surface of the terminal substrate (12), wherein vias (13) are arranged in the terminal substrate, which connect external contacts (15) arranged on an external contact side to terminal faces formed as internal contacts (14) on the contact surface of the terminal substrate, wherein terminal faces of the chips, which are arranged adjacent to the lateral edge, are connected to the internal contacts of the terminal substrate by way of a re-melted solder material deposit (16). Furthermore, the invention relates to a method for producing a chip arrangement (18).