H01L2224/16135

Semiconductor device

A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a first dielectric over the semiconductor substrate. The semiconductor device also includes a conductive layer disposed in the first dielectric and a second dielectric disposed on the conductive layer. In the semiconductor device, at least a portion of the conductive layer is exposed from the first dielectric and second dielectric. The semiconductor device further includes a conductive trace partially over the second dielectric and in contact with the exposed portion of the conductive layer. In the semiconductor device, the conductive trace is connected to the conductive pad at one end.

Substrate bonding method

A substrate bonding method includes: providing a first and a second substrate; forming, on the first substrate, a first metal micro-bump array including first metal pillar(s) formed on the first substrate and first metal nanowires formed thereon and spaced apart from each other; forming, on the second substrate, a second metal micro-bump array including second metal pillar(s) formed on the second substrate and second metal nanowires formed thereon and spaced apart from each other; pressing the first substrate onto the second substrate, such that the first and second metal micro-bump arrays are positioned and staggered with each other, forming a physically interwoven interlocking structure between the first and second metal nanowires; applying a filling material between the first and second substrates; curing the filling material to form a bonding cavity; and then performing confined heating reflux on the first and second metal micro-bump arrays in the bonding cavity.

Semiconductor chip package having underfill material surrounding a fan-out package and contacting a stress buffer structure sidewall

A fan-out package includes at least one semiconductor die attached to an interposer structure. a molding compound die frame laterally surrounding the at least one semiconductor die and including a molding compound material, and at least one stress buffer structure located on the interposer structure and including a stress buffer material having a first Young's modulus. The molding compound die frame includes a molding compound material having a second Young's modulus that is greater than the first Young's modulus.

SEMICONDUCTOR CHIP PACKAGE HAVING UNDERFILL MATERIAL SURROUNDING A FAN-OUT PACKAGE AND CONTACTING A STRESS BUFFER STRUCTURE SIDEWALL

A fan-out package includes at least one semiconductor die attached to an interposer structure, a molding compound die frame laterally surrounding the at least one semiconductor die and including a molding compound material, and at least one stress buffer structure located on the interposer structure and including a stress buffer material having a first Young's modulus. The molding compound die frame includes a molding compound material having a second Young's modulus that is greater than the first Young's modulus.

Semiconductor structure, stacked structure with terminal comprising capping layer and manufacturing method thereof

A semiconductor structure includes a semiconductor die, a redistribution circuit structure, and a terminal. The redistribution circuit structure is disposed on and electrically coupled to the semiconductor die. The terminal is disposed on and electrically coupled to the redistribution circuit structure, where the redistribution circuit structure is disposed between the semiconductor die and the terminal, and the terminal includes an under-bump metallization (UBM) and a capping layer. The UBM is disposed on and electrically coupled to the redistribution circuit structure, where the UBM includes a recess. The capping layer is disposed on and electrically coupled to the UBM, where the UBM is between the capping layer and the redistribution circuit structure, and the capping layer fills the recess of the UBM.